This 90 minutes tutorial gives a basic introduction to the UML Pro le for MARTE (Modeling and Analysis of Real-Time and Embedded systems) adopted by the Object Management Group. After a brief introduction to the UML pro ling mechanism, we give a broad overview of the MARTE Pro le. Then, the tutorial shall focus on the time model of MARTE and its companion language CCSL (Clock Constraint Speci cation Language).
The targeted audience is academics or industrials interested in high-level modeling with UML and its application to the analysis of real-time and embedded systems.
The tutorial does not require any preliminary background as it will give a high-level and broad description of the UML Pro le as well as a closer focus on its time model. To ensure that a large public can follow the presentation, we should start by a brief overview of UML light-weight extension mechanism, the so-called pro ling mechanism.
The Hardware Resource Modeling (HRM) package, which specializes the concepts of GCM into hardware devices such as processor, memory or buses, allows the modeling of the execution platforms in MARTE. The Allocation (Alloc) package allows the modeling of the space-time allocation of application functionality on an execution platform. Both the HRM and Alloc packages can be used with the RSM package for a compact modeling of repetitive hardware (e.g., grids of processing elements) and data and computation distributions of a parallel application onto such a repetitive hardware.
The models described with the previous packages can be re ned with
temporal properties speci ed within the Time package [
In MARTE, a clock c is a totally ordered set of instants, Ic. In the following, i and j are instants. A time structure is a set of clocks C and a set of relations on instants I = Sc2C Ic. ccsl considers two kinds of relations: causal and temporal ones. The basic causal relation is causality/dependency, a binary relation on I: 4 I I. i 4 j means i causes j or j depends on i. 4 is a pre-order on I, i.e., it is re exive and transitive. The basic temporal relations are precedence ( ), coincidence ( ), and exclusion (#), three binary relations on I. For any pair of instants (i; j) 2 I I in a time structure, i j means that the only acceptable execution traces are those where i occurs strictly before j (i precedes j). is transitive and asymmetric (re exive and antisymmetric). i j imposes instants i and j to be coincident, i.e., they must occur at the same execution step, both of them or none of them. is an equivalence relation, i.e., it is re exive, symmetric and transitive. i # j forbids the coincidence of the two instants, i.e., they cannot occur at the same execution step. # is irre exive and symmetric. A consistency rule is enforced between causal and temporal relations. i 4 j can be re ned either as i j or i j, but j can never precede i.
In this paper, we consider discrete sets of instants only, so that the instants of a clock can be indexed by natural numbers. For a clock c 2 C, and for any k 2 N?, c[k] denotes the kth instant of c.
Specifying a full time structure using only instant relations is not realistic
since clocks are usually in nite sets of instants. Thus, an enumerative
speci cation of instant relations is forbidden. The Clock Constraint Speci cation
Language (ccsl) de nes a set of time patterns between clocks that apply to
in nitely many instant relations [
The uml Pro le for marte proposes several speci c stereotypes in the Time
chapter to capture ccsl speci cations. Figure 2 brie y describes the three main
stereotypes. Boxes with the annotation metaclass denote the uml concepts
on which our pro le relies, so-called metaclasses. Boxes with stereotype are the
concepts introduced by marte, i.e., the stereotypes. Arrows with a lled head
represent extensions, whereas normal arrows indicate properties of the
introduced stereotypes. Clock extends uml Events to spot those events that can be
used as time bases to express temporal or logical properties. ClockConstraint
extends uml Constraints to make an explicit reference to the constrained clocks.
TimedProcessing extends Action to make explicit their start and nishing
events. When those events are clocks, then a ClockConstraint can constrain
the underlying action to start or nish its execution as de ned in a ccsl
specication.
On top of marte clocks, the Clock Constraint Speci cation Language de nes
a set of operators (relations and expressions) [
A ccsl speci cation consists of clock declarations and conjunctions of clock relations between clock expressions. A clock expression de nes a set of new clocks from existing ones, most expressions deterministically de ne one single clock. An example of clock expression is delay (denoted $: C N? ! C). c $ n speci es that a new clock is created and is the exact image of c delayed for n instants: o = c $ n de nes a clock o 2 C such that 8k 2 N?; o[k] c[k + n].
By combining primitive relations and expressions, we derive a very useful clock relation that denotes a bounded precedence. lef t n right is equivalent to the conjunction of lef t right and right (lef t $ n). The special case, when n is equal to 1 is called alternation and is denoted lef t right (reads lef t alternates with right). 3
The uml Pro le for marte is dedicated to the modeling and analysis of
realtime and embedded systems. Its time model relies on a notion of clock borrowed
from the synchronous languages [
This work has been partially funded by the PRESTO Project (ARTEMIS-20101-269362).
Frederic Mallet is an associate professor at Universite Nice Sophia Antipolis. He
is a permanent member of the Aoste team-project, a joint team between INRIA
and I3S laboratory. He received a PhD in Computer Science in 2000 and his
habilitation degree [