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  <front>
    <journal-meta />
    <article-meta>
      <title-group>
        <article-title>Unifying Patterns for Modelling Timed Relationships in Systems and Properties</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <string-name>Étienne André</string-name>
          <xref ref-type="aff" rid="aff0">0</xref>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Laure Petrucci</string-name>
          <xref ref-type="aff" rid="aff0">0</xref>
        </contrib>
        <aff id="aff0">
          <label>0</label>
          <institution>LIPN, CNRS UMR 7030, Université Paris 13</institution>
          ,
          <addr-line>Sorbonne Paris Cité</addr-line>
          ,
          <country country="FR">France</country>
        </aff>
      </contrib-group>
      <fpage>25</fpage>
      <lpage>40</lpage>
      <abstract>
        <p>Specifying the correctness of complex concurrent and realtime systems is a crucial problem. Many property languages have been proposed to do so; however, these techniques often involve formalisms not easily handled by engineers, and furthermore require dedicated tools. We propose here a set of patterns that encode common specification or verification components when dealing with concurrent real-time systems. We provide a formal semantics for these patterns, as time Petri nets, and show that they can encode previous approaches.</p>
      </abstract>
    </article-meta>
  </front>
  <body>
    <sec id="sec-1">
      <title>Introduction</title>
      <p>
        In the past few decades, many formal languages for specifying and verifying
complex concurrent and real-time systems have been proposed. However, these
formalisms are not always easy to handle by industry engineers. Temporal logics
(e.g. [
        <xref ref-type="bibr" rid="ref14 ref6">14,6</xref>
        ]) offer a very powerful way of expressing correctness properties for
concurrent systems but they are often considered too complicated (and maybe
too rich as well) to be widely adopted by engineers. Furthermore, they generally
need advanced tools dedicated to model checking.
      </p>
      <p>To overcome these difficulties, several pattern-based solutions have been
proposed. Patterns allow to identify frequent components of systems or properties
in a standardised manner and (sometimes) to compose them so as to build more
complex components. Here, we unify three sets of patterns proposed in the past.</p>
      <p>
        In [
        <xref ref-type="bibr" rid="ref11">11</xref>
        ], patterns are proposed for modelling scheduling problems; they are
then translated into timed automata [
        <xref ref-type="bibr" rid="ref4">4</xref>
        ]. In [
        <xref ref-type="bibr" rid="ref7">7</xref>
        ], tasks scheduling for operational
planning is tackled. A coloured Petri net [
        <xref ref-type="bibr" rid="ref10">10</xref>
        ] model is then derived. Both
works address the specification of systems [
        <xref ref-type="bibr" rid="ref11 ref7">11,7</xref>
        ] whereas [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ] proposes real-time
patterns for verification. These patterns are non-compositional, and do not aim
at exhaustiveness; on the contrary, they correspond to common correctness issues
met in the literature and in industrial case studies. They are translated to both
timed automata [
        <xref ref-type="bibr" rid="ref4">4</xref>
        ] and Stateful timed CSP [
        <xref ref-type="bibr" rid="ref15">15</xref>
        ] , and their verification reduces
to simple reachability checking.
      </p>
      <p>
        Contribution In this paper, we unify previous approaches to propose a
patternbased language for the specification of real-time systems and/or properties for
their verification. Each pattern has a syntax as human-readable as possible,
so that engineers non-experts in formal methods can use them. Furthermore,
we propose a Time Petri Net [
        <xref ref-type="bibr" rid="ref13">13</xref>
        ] semantics of these patterns for both system
models and properties. For verification, the patterns are thus translated into pure
reachability properties using simple observers, i.e. additional subsystems that
observe some system actions using synchronisation and may also use time. Hence,
their verification in practice avoids the use of complex verification algorithms or
dedicated tools, and tool developers can implement them at little cost.
      </p>
      <p>Our patterns can be used for two distinct purposes:
1. specify a system, by means of simple English-like constructs, rather than
using complex formalisms. Nevertheless the translation of our patterns into
time Petri nets provides a formal model of the system.
2. verify a system (not necessarily specified by our patterns), by means of the
same syntax. In this situation, our patterns are again translated into time
Petri nets, and can be used to verify the system model by synchronisation on
transitions, and using the sole reachability of some “bad” place. This avoids
the use of complex model checking algorithms.</p>
      <p>
        Even though the syntax is identical for both purposes, the translation into time
Petri nets for verification contains a few more places and transitions.
Related Work Concerning the specification of properties for verifying real-time
systems, temporal logics (e.g. [
        <xref ref-type="bibr" rid="ref14 ref6">14,6</xref>
        ]) and their timed extensions (e.g. [
        <xref ref-type="bibr" rid="ref3">3</xref>
        ] among
others) are by far the most commonly used, although many other formalisms
have been proposed. Much more expressive than our patterns, temporal logics
are more difficult to handle by non-experts. Furthermore, many tools do not
actually support their full expressiveness, but only some fragments.
      </p>
      <p>
        The idea of reducing (some) properties to reachability checking is not new:
in [
        <xref ref-type="bibr" rid="ref2">2</xref>
        ], safety and bounded-liveness properties are translated into test automata,
equivalent to our notion of observers. Among the differences are i) the fact
that we do not only verify but also specify systems using our patterns, and
ii) the fact that (as in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]) we exhibit commonly used patterns, whereas [
        <xref ref-type="bibr" rid="ref2">2</xref>
        ]
aims at completeness (the expressiveness of such reachability checking has been
characterised in [
        <xref ref-type="bibr" rid="ref1">1</xref>
        ]).
      </p>
      <p>
        In [
        <xref ref-type="bibr" rid="ref11">11</xref>
        ], typical temporal constraints dedicated to modelling scheduling
problems are identified, and then translated into timed automata. In [
        <xref ref-type="bibr" rid="ref12">12</xref>
        ], patterns for
specifying the system correctness are defined using UML statecharts, and then
translated into timed automata. As in our approach, their correctness reduces
to reachability checking. Differences include the choice of the target formalism
(time Petri nets for us) and the fact that our patterns can encode either the
system or its correctness property.
      </p>
      <p>
        Outline First, Section 2 recalls the earlier definitions of patterns we base on. We
then propose our new set of patterns in Section 3, and formalise them using time
Petri nets in Section 4. The patterns of [
        <xref ref-type="bibr" rid="ref11 ref5 ref7">11,7,5</xref>
        ] are encoded using our unified
patterns in Section 5. Finally, Section 6 concludes and gives perspectives for
future work.
      </p>
    </sec>
    <sec id="sec-2">
      <title>Earlier Works</title>
      <p>
        Earlier works we base on ([
        <xref ref-type="bibr" rid="ref11 ref5 ref7">11,7,5</xref>
        ]) are concerned on the one hand with causality
or timing relations between events, and on the other hand with patterns to
encode behavioural properties. Hence they address altogether different aspects
(model or property) that are nevertheless very intertwined.
2.1
      </p>
      <sec id="sec-2-1">
        <title>Scheduling Patterns [11]</title>
        <p>
          In [
          <xref ref-type="bibr" rid="ref11">11</xref>
          ], planning constraints are mapped into timed automata, using elementary
rules. A set of 17 interval-based temporal relations is defined. As in [
          <xref ref-type="bibr" rid="ref11">11</xref>
          ], we
group these 17 patterns in 6 categories.
        </p>
        <p>
          The temporal relations [
          <xref ref-type="bibr" rid="ref11">11</xref>
          ] allow for stating timing constraints between tasks.
These tasks are composed of two events, that are the start and the end of the
task. Time is often specified as an interval (d, D), to express that an event
happens between d and D units of time w.r.t. its reference.
        </p>
        <p>
          The temporal relations from [
          <xref ref-type="bibr" rid="ref11">11</xref>
          ] are the following ones (the words in brackets
are added in order to improve readability). The major ones (one per category)
are represented in Fig. 1.
        </p>
        <sec id="sec-2-1-1">
          <title>Task A</title>
        </sec>
        <sec id="sec-2-1-2">
          <title>Task A</title>
          <p>Task A
time
d1</p>
          <p>D1
d2</p>
          <p>D2
(e) A contains ((d1, D1)(d2, D2)) B
time
d1</p>
          <p>D1
d2</p>
          <p>D2</p>
          <p>
            time
(f) A
((d1, D1)(d2, D2)) B
parallels
As in [
            <xref ref-type="bibr" rid="ref11">11</xref>
            ], [
            <xref ref-type="bibr" rid="ref7">7</xref>
            ] was concerned with tasks scheduling for operational planning, each
task having a beginning and an end. Both of these can be timely related to those
of another task, as stated in the grammar and figures below.
// synchronisation between tasks
synch = BilateralSynch | UnilateralSynch
// lists of tasks
Tasks = task | Tasks, task
          </p>
          <p>The synchronisation between tasks can be either bilateral (the execution of
any of them is related to the execution of the others), or unilateral (the execution
of a task is related to that of the other one, but the converse is not true).</p>
          <p>
            In other words, in a bilateral synchronisation, all tasks occur or none of them
does. Note that in [
            <xref ref-type="bibr" rid="ref7">7</xref>
            ] tasks can synchronise either at their beginning (i.e. they
start together) or at their end (i.e. they finish at the same time). In this paper, we
will be interested in events (beginning or end) and not in a full task. Therefore,
bilateral synchronisation only specifies a set of interrelated events.
BilateralSynch = BILATERALSYNCH(Tasks)
          </p>
        </sec>
        <sec id="sec-2-1-3">
          <title>Task A</title>
          <p>time</p>
          <p>Fig. 2 depicts the bilateral synchronisation BILATERALSYNCH(A,B).</p>
          <p>When the synchronisation is unilateral, a task occurs w.r.t. either a timing
or another task, possibly with a delay.</p>
          <p>UnilateralSynch = Relation(task1, task2, delay)</p>
          <p>| Relation(task, delay)
Relation = AFTER | BEFORE | AT</p>
          <p>Examples in Fig. 3 depict the following relations:
(a) AT(A,10): task A starts at time 10;
(b) AFTER(A,10): task A starts after time 10;
(c) AT(A,B,15): task A begins 15 units of time after the end of task B;
(d) AFTER(A,B,10): task A begins at least 10 units of time after the end of
task B.
2.3</p>
        </sec>
      </sec>
      <sec id="sec-2-2">
        <title>Observer Patterns for Real-Time Systems</title>
        <p>
          In [
          <xref ref-type="bibr" rid="ref5">5</xref>
          ], we proposed a set of observer patterns encoding common properties
encountered when verifying concurrent real-time systems. These patterns are based
on observers, hence can be translated into pure reachability problems, thus
avoiding the use of complex verification algorithms. These patterns are
noncompositional, do not aim at completeness, but rather at exhibiting common
properties met in the case studies of the literature.
        </p>
        <p>The main patterns from this section are depicted in Fig. 4 where the arrows
show that the occurrence of an event implies the occurrence of the related event.
BeforeDeadline The first pattern relates an event with an absolute timing.
BeforeDeadline = a no later than d</p>
        <p>10
(a) AT(A,10)</p>
        <p>15
(c) AT(A,B,15)
time
10</p>
        <p>(b) AFTER(A,10)</p>
        <sec id="sec-2-2-1">
          <title>Task A Task A</title>
          <p>time
time</p>
          <p>an
time
time
time
a1
10
(d) AFTER(A,B,10)
a2
time
a1
a2</p>
        </sec>
        <sec id="sec-2-2-2">
          <title>Task A Task A a a1</title>
          <p>d time
(a) BeforeDeadline
(b) Precedence
(c) EventualResponse
(d) Sequence
Precedence The following patterns allow for expressing the precedence of the
current event by another, with or without an explicit time frame.</p>
          <p>The cyclic version of these patterns denotes that a pattern is repeatedly
valid, whereas in the strict cyclic version the pattern is not only repeatedly
valid, but no event mentioned in the pattern can happen in between (i.e. the
events mentioned in the pattern are alternating).</p>
          <p>The precedence pattern requires that, whenever event a2 happens, then
the event a1 must have happened before (at least once). Note that a2 is not
required to happen. In the CyclicPrecedence pattern, every time a2 happens,
then the event a1 must have happened before (at least once) since the last
occurrence of a2. In the strict cyclic version, every time a2 happens, then event
a1 must have happened exactly once since the last occurrence of a2, i.e. a1 and
a2 alternate. (They do not need to alternate forever though.) For example, in
the CyclicPrecedence, the sequence a1 a1 a2 can happen but not a1 a2 a2,
while in the StrictCyclicPrecedence none of them can happen.</p>
          <p>This pattern is extended to a timed version in a straightforward manner.
Precedence = if a2 then a1 has happened before
CyclicPrecedence = everytime a2 then a1 has happened before
StrictCyclicPrecedence = everytime a2 then</p>
          <p>a1 has happened exactly once before
Response Expressing that the current event will be followed by a response is
formulated by the following pattern. This pattern is equivalent to the
“eventually” in linear temporal logics. None of the two events is required to happen;
however, if the first one does, then second must eventually happen too. The cyclic
and strictly cyclic versions are defined as for precedence. A timed extension (as
in timed temporal logics) is also defined.</p>
          <p>EventualResponse = if a1 then eventually a2
CyclicEventualResponse = everytime a1 then eventually a2
StrictCyclicEventualResponse = everytime a1 then</p>
          <p>eventually a2 once before next a1
TimedResponse = if a1 then eventually a2 within d
CyclicTimedResponse = everytime a1 then eventually a2 within d
StrictCyclicTimedResponse = everytime a1 then
eventually a2 within d
once before next a1
Sequence Events can also be ordered as a sequence. None of the n events is
required to happen; however, if some (or all) do, then they must follow exactly
the order defined by the sequence. The cyclic version is straightforward. However,
no strict cyclic version is defined, as it would be identical to the cyclic version.
Sequence = SEQUENCE a1, ..., an
CyclicSequence = always SEQUENCE a1, ..., an
eventlist =</p>
          <p>eventlist EVENT
| EVENT
interval = (d, D) | [d, D] | [d, D) | (d, D]
timing = WITHIN interval
simplePattern =</p>
          <p>EVENT AT timing
| EVENT EVENTUALLY timing EVENT
| EVENT timing AFTER EVENT
| SEQUENCE (eventlist)
pattern =</p>
          <p>pattern OR simplePattern
| pattern AND simplePattern
| ALWAYS simplePattern
| simplePattern
SYNTACTIC SUGAR:</p>
          <p>
            AT LEAST d = WITHIN [d, infinity)
AT MOST d = WITHIN [0, d]
EXACTLY d = WITHIN [d, d]
Unreachability The last pattern of [
            <xref ref-type="bibr" rid="ref5">5</xref>
            ] is rather different from others, as it
only expresses the model safety (i.e. non-reachability of a undesired state). It
was considered in [
            <xref ref-type="bibr" rid="ref5">5</xref>
            ] because this property is by far the most commonly met in
case studies from the literature, and because all other patterns can be reduced
to (non-)reachability.
          </p>
          <p>Unreachable = UNREACHABLE(Bad)
3</p>
        </sec>
      </sec>
    </sec>
    <sec id="sec-3">
      <title>Towards a More Complete Patterns Language</title>
      <p>
        The primitives in the grammars of Section 2.1 and Section 2.2 are dedicated
to temporal or causal relations between tasks which are characterised by both
their starting and ending times. But, in practice, most systems are concerned
with individual events, as is the case in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]. We present in this section a unified
version of patterns previously introduced. We will show in Section 5 that our
patterns subsume the primitives from Section 2.
      </p>
      <p>We introduce a grammar for unified patterns Fig. 5. Our grammar considers
individual events that can form a list of events in order to construct a sequence.
The timing of events can be specified as being within a time frame (from d to
D time units, where d ∈ R+ and D ∈ R+ ∪ {∞}). The only restriction is that
the interval [d, D] 6= [0, ∞) (see Remark 1 infra).</p>
      <p>Simple patterns express basic relations between individual events. An event
can happen w.r.t. an absolute timing constraint. An event can eventually entail
the occurrence of another event w.r.t. some timing constraint. Conversely, an
event can occur only w.r.t. a timing after another event already occurred. Events
can be ordered in a sequence, thus all occurring one after another.
Simple Patterns The simple patterns contain four kinds of relationships, that
we describe in more details in the following.</p>
      <p>The pattern fragment EVENT AT encodes an absolute timing; it is used to
describe events that must happen exactly at an (absolute) time.</p>
      <p>The pattern fragment EVENT EVENTUALLY timing EVENT encodes that,
whenever the first event happens, then the second will eventually happen, with
the timing constraint specified by timing. That is, if the first event happens,
the second must happen. The converse is not true: if the second event happens,
the first one did not necessarily happen before.</p>
      <p>The pattern fragment EVENT timing AFTER EVENT encodes that, whenever
the first event happens it is necessarily after the second one, together with some
timing constraint. For example, e2 WITHIN(d,D) AFTER e1 denotes that e2 may
or may not happen, but if e2 happens, then it must be at least d and at most D
time units after the first occurrence of e1. Also note that, if e2 does not happen,
then e1 may or may not happen.</p>
      <p>Finally, the SEQUENCE ensures that a list of events happen in the particular
order specified.</p>
      <p>Complex Patterns Patterns can be combined in order to form more complex
ones. First, we can use Boolean AND and OR operators to express the conjunction
of patterns (i.e. both must be executed, for patterns expressing systems, or must
be valid, for patterns expressing the properties) or the disjunction (i.e. either
one of them can be executed/valid).</p>
      <p>
        The ALWAYS is a sort of fixpoint, with a semantics similar as the notion of
“cyclic” pattern in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]. That is, once the pattern has been executed / verified, then
it must again be executed / verified. This typically describes a cyclic behaviour.
We restrict here the ALWAYS pattern to simple patterns (simple pattern in
Fig. 5 ant not, e.g. pattern). The reason is on the one hand to keep our language
simple1, and on the other hand to make a translation to time Petri nets relatively
easy.
      </p>
      <p>Finally, it is often convenient to use some syntactic sugar for expressing
timing constraints: AT LEAST, AT MOST and EXACTLY.</p>
      <p>
        Remark 1 (untimed patterns). We could encode untimed patterns using our
timed patterns (by allowing a syntactic sugar construct UNTIMED = WITHIN [0,
1 Furthermore, while designing the patterns in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ], such ALWAYS-like properties were
only encountered in the literature on (very) simple patterns.
infinity)), but we leave it out so as to keep the exposé simple. Indeed, although
this does not bring theoretical problems, the translation of the untimed patterns
into time Petri nets for verification purposes then exceeds the set of properties
that can be checked using sole unreachability. In particular, the negation of the
untimed “eventually” construct cannot be checked using the unreachability of
a “bad” state, but it becomes necessary to additionally check the reachability
of some “good state”; this was performed in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]. Here, to keep the translation
simple, we temporarily leave out the untimed patterns. Formalising the untimed
patterns for the verification purpose will be performed in an extended version of
this work.
4
      </p>
    </sec>
    <sec id="sec-4">
      <title>Semantics: Translation to Time Petri Nets</title>
      <p>
        Time Petri nets [
        <xref ref-type="bibr" rid="ref13">13</xref>
        ] are Petri nets where transition are equipped with a time
interval, that specifies the minimum and maximum time for the transition to
be enabled before it actually fires. The different patterns in the grammar of
Fig. 5 are modelled as time Petri nets in Fig. 6a–6h. Let us now describe our
translation. We start with simple (i.e. non-compositional) patterns, and then go
for complex patterns (i.e. that rely on others).
      </p>
      <p>
        Observers Let us recall the concept of observers, as formalised in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]. Observers
are standard subsystems, with some assumptions. An observer must not have any
effect on the system, and must not prevent any behaviour to occur. In particular,
it must not block time, nor prevent actions to occur, nor create deadlocks that
would not occur otherwise. As a consequence, observers must be complete: in
the example of timed automata, all actions declared by the observer must be
allowed in any of the locations. Similarly, in time Petri nets, an observer must
be able to synchronise at any time with any of the actions used on its transitions.
General Idea of our Translation Recall that our patterns aim at encoding both
systems and properties. Although they are defined in a unified manner in
Section 3, they must be differentiated when formalised using time Petri nets. Indeed,
our patterns seen as properties reduce verification to simple reachability analysis
(as in [
        <xref ref-type="bibr" rid="ref1 ref2 ref5">2,1,5</xref>
        ]).
      </p>
      <p>For the verification, we define a “bad” place (labelled in Fig. 6a–6h using
the “/” symbol); this place is assumed to be unique, i.e. one must fuse all
occurrences of this place when composing patterns. The verification can then be
carried out as follows: given a model of the system specified using time Petri
nets (but not necessarily specified using our specification patterns), and given a
property of the system specified using our patterns and translated into a time
Petri nets, we perform the synchronisation (on transitions) of the entire system.
Then, the property (expressed by the pattern) is satisfied iff the “ /” place is
unmarkable, i.e. cannot be marked in any marking of the synchronised net.</p>
      <p>In order to differentiate between the specification of systems and the
specification of properties, we depict in dotted red the places and transitions necessary
to add to our translated patterns so as to be able to perform verification. In
other words, these dotted red places and transitions shall be omitted when
specifying systems and not properties. Conversely, we depict in plain light blue the
places and transitions only necessary for the system specification, but that must
be omitted for the verification.</p>
      <p>A1
A2</p>
      <p>Fig. 6: Translation of our patterns into time Petri nets
Simple Patterns Fig. 6a gives the translation of the A AT WITHIN (d, D)
pattern. For the property, the translation is straightforward: a place is followed by
a timed transition with firing time [d, D] labelled with A. This correctly encodes
the fact that A must occur within [d, D] after the system start. (We assume
closed intervals in the remainder of the translation; open or semi-open intervals
can be handled similarly.) Concerning the verification, in addition to the
correct behaviour, we need also to specify the bad behaviour, hence in this case
another transition that can occur only if the timing is not satisfied, leading to
the “bad” place. That is, the bad place is reachable iff the property is violated.
Additionally, for our pattern to be a good “observer” (i.e. that must not
disturb the system), it must be able to synchronise at any time with the system
on the transition the pattern declares (here only A). This explains the loop on
transition A on the right-hand side of Fig. 6a. (In fact, self-loops should also be
added to the bad place; we omit them for sake of space, but also because it is
less important to block the system once the property has been proved invalid.)</p>
      <p>Pattern A1 EVENTUALLY WITHIN (d, D) A2 is modelled by the TPN in
Fig. 6b. For the specification, two cases are admitted: one where A1 is fired,
and one where it is not. Moreover the possibility of firing A1 depends on other
actions in the system which may put a token in the initial place of the pattern
(depicted by an incoming arrow). The additional places and transitions for the
verification counterpart of this pattern are explained as follows: the first
selfloop allows A2 to happen anytime as long as A1 has not happened. Then, if A2
happens strictly before or strictly after [d, D], the observer enters the bad place.
Otherwise, the property is satisfied, and both A1 and A2 can happen anytime,
which is depicted using the two self-loops.</p>
      <p>The A2 WITHIN (d, D) AFTER A1 pattern (given in Fig. 6c) is similar to the
previous one but, in this case, it is not possible to have A2 without A1. As for the
verification, note that A2 cannot occur before A1, hence the transition between
the initial place and the bad place. Furthermore, several A1 may occur before A2
occurs: this is encoded using the second output from A1 and a self-loop. Thus
the time for firing A2 is counted from the first occurrence of A1. The rest of the
pattern is similar to the previous one.</p>
      <p>The SEQUENCE(A1,A2,...,An) pattern is given in Fig. 6h. Naturally, it is
made of a sequence of transitions. Additionally, the verification version is such
that, as soon as a transition violates the order imposed by the sequence, the
system goes to the bad place. An additional self-loop in the last good place,
synchronising on any transition, makes the observer non-blocking.
Complex Patterns These patterns are used to combine the previous ones
(eventually with complex patterns as well). In Fig. 6d to Fig. 6g, they are pictured in
dashed boxes, which would also include the “bad” place. For the specification, the
complex patterns are straightforward: they syntactically combine existing
patterns. For the verification, this is a little less simple: first, recall that all “bad”
locations must be fused into a single one. Second, the “and” verification pattern
becomes identical to the. . . “or” specification pattern: this is because the
property P1 AND P2 is violated if P1 is violated (i.e. the bad place is reachable in the
corresponding pattern) or P2 is violated. The “or” pattern is not translated for
verification; this is because this cannot be checked with sole unreachability (see
Section 6). Concerning the ALWAYS pattern for verification, one must fuse the
last non-dotted place of the pattern (usually the right-most place in the figures)
with the initial place. However, the self-loops (generally on A1 and A2) on the
last non-dotted place must be removed.</p>
      <p>Initial Marking In addition to the tokens introduced by the absolute time
patterns (A AT WITHIN (d,D)), a single initial token must be put in the top-most
pattern of the composed pattern expression. (We assume that, if the top-most
expression is a pattern A AT WITHIN (d,D), then no further token is added.)
5</p>
    </sec>
    <sec id="sec-5">
      <title>Encoding Previous Patterns Using our Unified Patterns</title>
      <p>In this section we show how all primitives from Section 2 can be expressed using
our new set of patterns.</p>
      <p>In order to express the relations between tasks described in Section 2.1 and
Section 2.2 with these new primitives, a task A is transformed into two events,
specifying the task Beginning (A.start) and its end (A.end).
5.1</p>
      <sec id="sec-5-1">
        <title>Encoding Patterns from [11]</title>
        <p>The expression of patterns from Section 2.1 is summarised in Table 1.</p>
        <p>Note that several rules are expressed identically. For example, rule 2 is
reflecting the point of view from event A, and rule 4 the one of event B, while in
our patterns we express the relation as seen from an external observer.
5.2</p>
      </sec>
      <sec id="sec-5-2">
        <title>Encoding Patterns from [7]</title>
        <p>Table 2 shows the mapping for the patterns of Section 2.2.</p>
        <p>Note that formula 5 implies that if B does not occur, neither does A. On the
contrary, if B occurs, A can occur or not. If it does, it is d units of time after B
ended. A similar remark applies to formula 6. Finally, in formula 7, A necessarily
occurs d units of time after the end of B.
5.3</p>
      </sec>
      <sec id="sec-5-3">
        <title>Encoding Patterns from [5]</title>
        <p>
          Patterns from Section 2.3 are presented in Table 3. Our translation is
straightforward. The only “trick” is the translation of the “strict cyclic” patterns of [
          <xref ref-type="bibr" rid="ref5">5</xref>
          ],
that are encoded using both the cyclic version of these patterns (using ALWAYS)
and the SEQUENCE pattern, that requires A1 and A2 to alternate.
6
        </p>
      </sec>
    </sec>
    <sec id="sec-6">
      <title>Conclusion</title>
      <p>
        We proposed a unified pattern mechanism to both specify and verify real-time
systems, together with a semantics using time Petri nets. Our new set of patterns
unifies the patterns of [
        <xref ref-type="bibr" rid="ref11 ref5 ref7">11,7,5</xref>
        ] into a single homogeneous pattern language.
Future Works First, translating the untimed EVENTUALLY and the OR patterns
for verification purposes is in our agenda; this will be done by checking, not only
the unreachability of the bad, but also the reachability of a good place.
      </p>
      <p>
        Second, more patterns from the literature should be integrated to our
encoding. Although we shall not develop too complex a pattern system, so as to avoid
giving birth to a complicated property language, the patterns in [
        <xref ref-type="bibr" rid="ref12">12</xref>
        ] seem
interesting to us. Furthermore, the patterns of [
        <xref ref-type="bibr" rid="ref9">9</xref>
        ] seem to fit directly in our unified
pattern systems, but this should be shown formally. It would also be interesting
to formally compare the expressiveness of our patterns with [
        <xref ref-type="bibr" rid="ref1 ref2">2,1</xref>
        ] or (subsets of)
temporal logics such as LTL/CTL.
      </p>
      <p>
        Third, although it is relatively easy to convince oneself that we correctly
encoded the patterns of [
        <xref ref-type="bibr" rid="ref11 ref5 ref7">11,7,5</xref>
        ], formally proving their semantic equivalence
would be interesting. It would also be nice to provide tool support, helping a
designer to write patterns to model a system and its properties.
      </p>
      <p>
        Finally, our translation to time Petri nets was done manually. An alternative
option would be to define an ad-hoc domain specific language (DSL), and then
to use model transformation techniques (such as in [
        <xref ref-type="bibr" rid="ref8">8</xref>
        ]) to obtain time Petri nets.
      </p>
      <sec id="sec-6-1">
        <title>Acknowledgement</title>
        <p>We are grateful to the anonymous reviewers for useful comments.
Formula 1 BILATERALSYNCH(A,B) A.start EXACTLY 0 AFTER B.start</p>
        <p>OR A.end EXACTLY 0 AFTER B.end
Formula 2 AT(A,d) A.start AT EXACTLY d
Formula 3 AFTER(A,d) A.start AT AT LEAST d
Formula 4 BEFORE(A,d) A.start AT AT MOST d
Formula 5 AT(A,B,d) A.start EXACTLY d AFTER B.end
Formula 6 AFTER(A,B,d) A.start AT LEAST d AFTER B.end
Formula 7 BEFORE(A,B,d) B.end EVENTUALLY AT MOST d A.start</p>
        <p>
          Table 2: Encoding patterns from [
          <xref ref-type="bibr" rid="ref7">7</xref>
          ]
A
1
)
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1
5 4 3 2 1 0
C S e S e C i T e S e C i T B e S e C E e S C P
y e v t v y f i v t v y f i e v t v y v v t y r
c q e r e c m e r e c m f e r e c e e r c e
l u r i r l A e r i r l A e o r i r l n r i l c
i e y c y i 1 d a y c a y i 2 d r y c y i t y c i e
c n t t t c R t t t t t c P e t t t c u t t c d
S c i C i T t e i C i T t r D i C i E a i C P e
e e m y m i h s m m y m m i h e e m y m v l m y r n
q e c e m e p o e c o e m e c a e c e e R e c e c
u = l e n o s l s e n e d l n e l c e
e A i A d n t A i t A d d l A i A t s A i e
n s 1 c 1 R e s 2 c 2 P A e i 1 c 1 u p 2 c d =
c e T e v e d T d r 1 n n E a o P e
e q t i t s e t i t e c e t v t l n t r n i
u h m h p n = u h m u h c h e h e h R s h e c f
= e e e e o t n e e n e e a = e n e e e e c e
n n d n n u i n d i n d s = n t n s n e A
a c R s a t P t e A u p = d = 2
l e e e e e l s A r s A n h e a e o A e
w v s v l 1 e 1 c a n v l v n i 1 n e t
a A e p e = y o c o e p o e R e s f c v h
y 1 n o n f h e f h p n e n e h e e e
s , t n t A a d a = e l t s t A a r n
u s u 2 t s e t s n a u p u = 1 s = y
s . a e a i n i e t a o a t A
e . l l w m h c m h d e l n l t h i 1
q . l = l i e a e e a r l s l h a m
u , y y t p p a y e y e p e h
e h b p = b p t t n p a
n A A A i e e e e h A = A e A s
T c n 2 2 n f n f n m a 2 2 e n 2
a e o e o e o n v e h
b w w d r d r d s o ( e d t a
l A i i e e t d n b n h p
e 1 t t e c e t e e p
, h h x d e f u x n e
3 i i a o a a n
: . n n c u b r l c A e
E . t n e e l t 1 d
n ., d d ly it fo n y ly h b
c o s r e A a e
o A n o e x 2 o s f
d n c n o t n o
in e ce f ne A ce ha re
g b t x 1 p
p e i t ) b p
f m e e
a o e A f n
tte re 1 or ed
r e
n
        </p>
      </sec>
    </sec>
  </body>
  <back>
    <ref-list>
      <ref id="ref1">
        <mixed-citation>
          1.
          <string-name>
            <given-names>Luca</given-names>
            <surname>Aceto</surname>
          </string-name>
          , Patricia Bouyer, Augusto Burgueño, and Kim Guldstrand Larsen.
          <article-title>The power of reachability testing for timed automata</article-title>
          .
          <source>In Vikraman Arvind and Ramaswamy Ramanujam</source>
          , editors,
          <source>FSTTCS</source>
          , volume
          <volume>1530</volume>
          <source>of LNCS</source>
          , pages
          <fpage>245</fpage>
          -
          <lpage>256</lpage>
          . Springer,
          <year>1998</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref2">
        <mixed-citation>
          2.
          <string-name>
            <given-names>Luca</given-names>
            <surname>Aceto</surname>
          </string-name>
          , Augusto Burgueño, and Kim G. Larsen.
          <article-title>Model checking via reachability testing for timed automata</article-title>
          .
          <source>In TACAS</source>
          , volume
          <volume>1384</volume>
          <source>of LNCS</source>
          , pages
          <fpage>263</fpage>
          -
          <lpage>280</lpage>
          . Springer,
          <year>1998</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref3">
        <mixed-citation>
          3.
          <string-name>
            <given-names>Rajeev</given-names>
            <surname>Alur</surname>
          </string-name>
          , Costas Courcoubetis,
          <string-name>
            <given-names>and David L.</given-names>
            <surname>Dill</surname>
          </string-name>
          .
          <article-title>Model-checking in dense real-time</article-title>
          .
          <source>Information and Computation</source>
          ,
          <volume>104</volume>
          (
          <issue>1</issue>
          ):
          <fpage>2</fpage>
          -
          <lpage>34</lpage>
          ,
          <year>1993</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref4">
        <mixed-citation>
          4.
          <string-name>
            <given-names>Rajeev</given-names>
            <surname>Alur</surname>
          </string-name>
          and
          <string-name>
            <given-names>David L.</given-names>
            <surname>Dill</surname>
          </string-name>
          .
          <article-title>A theory of timed automata</article-title>
          .
          <source>Theoretical Computer Science</source>
          ,
          <volume>126</volume>
          (
          <issue>2</issue>
          ):
          <fpage>183</fpage>
          -
          <lpage>235</lpage>
          ,
          <year>1994</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref5">
        <mixed-citation>
          5.
          <string-name>
            <given-names>Étienne</given-names>
            <surname>André</surname>
          </string-name>
          .
          <article-title>Observer patterns for real-time systems</article-title>
          .
          <source>In ICECCS</source>
          , pages
          <fpage>125</fpage>
          -
          <lpage>134</lpage>
          . IEEE Computer Society,
          <year>2013</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref6">
        <mixed-citation>
          6.
          <string-name>
            <given-names>Christel</given-names>
            <surname>Baier</surname>
          </string-name>
          and
          <string-name>
            <surname>Joost-Pieter Katoen</surname>
          </string-name>
          .
          <article-title>Principles of model checking</article-title>
          . MIT Press,
          <year>2008</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref7">
        <mixed-citation>
          7.
          <string-name>
            <given-names>Sébastien</given-names>
            <surname>Bardin</surname>
          </string-name>
          and
          <string-name>
            <given-names>Laure</given-names>
            <surname>Petrucci</surname>
          </string-name>
          .
          <article-title>COAST : des réseaux de Petri à la planification assistée</article-title>
          .
          <source>In AFADL</source>
          , pages
          <fpage>285</fpage>
          -
          <lpage>298</lpage>
          ,
          <year>2004</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref8">
        <mixed-citation>
          8.
          <string-name>
            <surname>Julien</surname>
            <given-names>DeAntoni</given-names>
          </string-name>
          , Papa Issa Diallo, Ciprian Teodorov, Joël Champeau, and
          <string-name>
            <given-names>Benoît</given-names>
            <surname>Combemale</surname>
          </string-name>
          .
          <article-title>Towards a meta-language for the concurrency concern in DSLs</article-title>
          . In DATE, pages
          <fpage>313</fpage>
          -
          <lpage>316</lpage>
          . ACM,
          <year>2015</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref9">
        <mixed-citation>
          9.
          <string-name>
            <given-names>Jin</given-names>
            <surname>Song</surname>
          </string-name>
          <string-name>
            <surname>Dong</surname>
          </string-name>
          , Ping Hao, Shengchao Qin, Jun Sun, and
          <string-name>
            <given-names>Wang</given-names>
            <surname>Yi</surname>
          </string-name>
          .
          <article-title>Timed automata patterns</article-title>
          .
          <source>IEEE Transactions on Software Engineering</source>
          ,
          <volume>34</volume>
          (
          <issue>6</issue>
          ):
          <fpage>844</fpage>
          -
          <lpage>859</lpage>
          ,
          <year>2008</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref10">
        <mixed-citation>
          10.
          <article-title>Kurt Jensen and Lars Michael Kristensen</article-title>
          .
          <source>Coloured Petri Nets - Modelling and Validation of Concurrent Systems</source>
          . Springer,
          <year>2009</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref11">
        <mixed-citation>
          11.
          <string-name>
            <surname>Lina</surname>
            <given-names>Khatib</given-names>
          </string-name>
          , Nicola Muscettola, and
          <string-name>
            <given-names>Klaus</given-names>
            <surname>Havelund</surname>
          </string-name>
          .
          <article-title>Mapping temporal planning constraints into timed automata</article-title>
          .
          <source>In TIME</source>
          , pages
          <fpage>21</fpage>
          -
          <lpage>27</lpage>
          . IEEE Computer Society,
          <year>2001</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref12">
        <mixed-citation>
          12.
          <string-name>
            <surname>Ahmed</surname>
            <given-names>Mekki</given-names>
          </string-name>
          , Mohamed Ghazel, and
          <string-name>
            <given-names>Armand</given-names>
            <surname>Toguyeni</surname>
          </string-name>
          .
          <article-title>Validating timeconstrained systems using UML statecharts patterns and timed automata observers</article-title>
          .
          <source>In VECoS</source>
          , pages
          <fpage>112</fpage>
          -
          <lpage>124</lpage>
          . British Computer Society,
          <year>2009</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref13">
        <mixed-citation>
          13.
          <string-name>
            <surname>Philip Meir Merlin</surname>
          </string-name>
          .
          <article-title>A study of the recoverability of computing systems</article-title>
          .
          <source>PhD thesis</source>
          , University of California, Irvine,
          <year>1974</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref14">
        <mixed-citation>
          14.
          <string-name>
            <given-names>Amir</given-names>
            <surname>Pnueli</surname>
          </string-name>
          .
          <article-title>The temporal logic of programs</article-title>
          .
          <source>In FOCS</source>
          , pages
          <fpage>46</fpage>
          -
          <lpage>57</lpage>
          . IEEE Computer Society,
          <year>1977</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref15">
        <mixed-citation>
          15.
          <string-name>
            <surname>Jun</surname>
            <given-names>Sun</given-names>
          </string-name>
          , Yang Liu, Jin Song Dong, Yan Liu, Ling Shi, and
          <string-name>
            <given-names>Étienne</given-names>
            <surname>André</surname>
          </string-name>
          .
          <article-title>Modeling and verifying hierarchical real-time systems using Stateful Timed CSP</article-title>
          .
          <source>ACM Transactions on Software Engineering and Methodology</source>
          ,
          <volume>22</volume>
          (
          <issue>1</issue>
          ):
          <fpage>3</fpage>
          .
          <fpage>1</fpage>
          -
          <lpage>3</lpage>
          .
          <fpage>29</fpage>
          ,
          <year>2013</year>
          .
        </mixed-citation>
      </ref>
    </ref-list>
  </back>
</article>