Reliability effects are real threats with advanced process nodes. This paper describes the industrial challenges associated with accurate modeling of aging problems. Joint design-reliability flows can mitigate their effects, and allow designers to take those effects into account as early as possible.
Advanced short-geometry CMOS processes are subject to aging that causes major reliability issues, degrading the performance of integrated circuits over time. Degradation effects causing aging are hot carrier injection (HCI) and negative bias temperature instability (NBTI), in addition to positive bias temperature instability (PBTI) and time dependent dielectric breakdown (TDDB). Below 90 nm, consideration of these effects is becoming mandatory for design flows targeting quality and reliability. This paper describes the state-of-the-art simulation flow that can help designers address these issues and to create more reliable designs.
These particular reliability effects modify the
fundamental behavior of the transistors, such as threshold
voltage (Vth) and the mobility factor [
Figure 1 Reliability bathtub and the effect of new node introduction.
II.
c)
It would be obvious that for new technology nodes the
wear out failure curve shifts to the left, which means earlier
device degradation as shown in Figure 1 [
Each device experiences a different stress that depends on
its exact individual bias conditions, in addition to global
conditions such as temperature. This stress is computed
individually and integrated over a particular time window
[
This stress quantity is then used to compute degraded Wear Out values of the model parameters (such as the threshold, mobility, etc.). Using these degraded model parameters, a new simulation is run which represents what would happen after N years of operation. In this aged simulation, each device uses its own individual degraded model with updated Vth, mobility etc., because the stress is device-specific and Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Co-Located with DATE 2016 - Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors. so is the update. Fresh and aged simulation results can be overlapped and compared.
Models can either take into account DC stress or dynamic
stress, including the recovery effect [
Although rather sophisticated, this entire process is now completely integrated in regular SPICE flows (Figure 2).
From the designer’s perspective, performing an aging analysis of a cell or circuit is just a new command in the simulator, and just as simple to use.
The computation of the stress and the update of the
electrical model parameters is done with user-defined
equations. These two sets of equations are called a stress
model and an update model. They can have virtually any
complexity, from the simplest two-lines-of-code model to a
pages-and-pages model. Examples of realistic models can
be shown in [
To further complicate an already difficult subject, aging appears to be a statistical process unto itself. If you consider two identical devices drawn side-by-side, they will have slightly different (fresh) threshold voltages, drive current, and leakage currents. The distribution of these parameters is monitored by the foundries, allowing statistical simulations by designers. But, unfortunately, the same is true for their aging characteristics. Two identical devices with identical bias conditions do not age exactly in the same way. The Vth shift, for example, is a statistical variable with its own mean, variance, etc. This spread of the aged transistor parameters also will be reflected onto the measured performances such as a propagation time (see Figure 3) and distortion level.
However, the required measurements needed to capture the statistical nature of the aging process are much more complicated, lengthy, and costly than regular process monitoring.
Solid information about the statistical properties of the aging process is rarely available from the foundries however Eldo easily support statistical analysis on top of the aging flow. For example, it is possible to assign a certain variance to any of the parameters that define the aging models and run a Monte Carlo simulation to get a statistical view of the aging trajectories.
Reliability models are implemented in the Eldo UDRM
(User Defined Reliability Model) interface [
Reliability changes can be analyzed for any degradation effect: HCI, NBTI, PBTI and TDDB.
In a Long-Term Reliability Simulation Scheme, there are two possible methods: Two simulations scheme & Repetitive scheme In the Two simulations scheme the steps are as follows: 1. A transient simulation with the “fresh” device is done. 2. At the end of the fresh simulation, the amount of damage each device has been subjected to, caused by the stress applied on the device, is calculated. 3. The transistor models are updated accordingly using the equations specified in the user defined reliability functions. 4. A new transient simulation is run with the aged device.
In the Repetitive scheme, the long period Tage is divided into smaller time intervals Ti (where Tage=ΣTi).
The same steps as the two simulations scheme are followed, except that steps 2 to 4 are repeated NBRUN times, where NBRUN is the number of time intervals. The calculation of the stress is updated at the end of every time interval. This process is repeated until t=Tage. This approach can account for the gradual changing bias conditions as a result of device degradation. It is obvious that if the number of time divisions was chosen to be equal to one, the Repetitive scheme will be identical to the two simulations scheme. The more general case, the Repetitive scheme, is implemented in Eldo to ensure a high level of accuracy, and account for the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Co-Located with DATE 2016 - Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors. gradual changing bias conditions as a result of device degradation which could significantly affect the results. This flow is described in Figure 4.
Up to recently, aging mechanism has mainly focused on active devices. However, new challenges have appeared in industrial and automotive power applications where resistors and capacitor degradations are becoming critical issues. For example the need for accounting accurate resistors instability modeling has become mandatory in latest high voltage processes. Eldo has been addressing those new challenges while targeting any kind of design regions and not only blocks which contain transistors.
Furthermore, as Eldo can run electro-thermal simulation using an electrical netlist connected to a thermal netlist (built using RC network), one can mix those 2 capability to apply aging on the thermal RC components which are part of the simulated thermal network. Without this capability, an electro-thermal simulation considers that the RC thermal network does NOT degrade over time. Eldo can help to remove this limitation in applying degradation models for both the electrical and thermal netlists..
IV.
Using a joint design-reliability flow allows the designer to predict the behavior of the circuit versus “wall-clock” time. Important metrics can be traced versus time and verified against the specifications. For example, Figure 5 shows how the operating frequency of a CMOS oscillator degrades over time. The absolute period and the relative degradation (in %) of the frequency are shown in the upper and lower plots, respectively. The x-axis is the time in years in logarithmic scale. The frequency is degraded by nearly 5% after only one year of operation. The rest of the circuit may be able to accommodate such degradation, or not.
Predicting the degradation of a key metric (here it is an oscillation frequency, but it could be power consumption, a distortion level, or a settling time) is interesting. However, it is a compound result that depends on many variables. The next thing a designer wants to know is which device is primarily responsible for the degradation of the observed metric. Joint design-reliability flows allow identification of devices that are subject to the largest degradation. The information is typically presented in tabular format with sorting criteria. For example, a table may show the relative degradation of the drive current, the linear current, and also the trans-conductance (gm), Vth, or generally any quantity of interest. The designer can choose the sorting criterion. In the example shown in Figure 6, the results are sorted by decreasing “delta-Vth,” where the devices that have their threshold voltage degraded the most severely are presented first. This allows the designer to immediately identify the areas in the circuit that require extra attention.
IP protection is one of the main benefits of this flow. For many companies or foundries, the details of the equations and models used to predict degradation are not considered public information. Rather, they consider it to be sensitive proprietary information that they are not keen to disclose in any way. For this purpose, Eldo has developed encryption mechanisms that allow full protection of the information.
They can run the simulation using only binary non-human– readable model files. As well, security encryption keys can be used to restrict access and control the execution of the models by the simulators. Once encrypted and protected, only licensed partners, customers or sub-contractors, such as design houses, can make use of the protected libraries.
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Co-Located with DATE 2016 - Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors.
A complete use model of the flow starting from stress and
update model development, implementation in Eldo UDRM
interface and performing aging analysis on a design and
showing how the stress effects was crucial for the design is
described in [
M1 drain voltage switches from VDD to 0 following a 1
MHz square waveform while M2 is stressed in DC
conditions. M1 is stressed for half a period while in the
other half it is off and can partially recover the degradation.
Therefore after reliability simulation, M2 Vth will become
more negative than M1 one and comparator will switch at a
positive drain voltage given by Vth shifts difference in the
input stage MOS. This effect, which can’t be predicted
without the modelling of NBTI recovery, can generate
unacceptable reverse currents causing the failure of circuit
operation as observed in a real case. This has been
illustrated in [
Reliability effects are real threats with advanced process nodes, joint design–reliability flows, however, can mitigate their effects and allow designers to take those effects into account as early as possible.
Eldo provides a fully customizable and robust aging simulation interface that allows IP protection where details of the equations and models used to predict degradation can be encrypted to secure the IP.
This solution can be used with any type of analysis: AC, DC, Transient, RF, statistics, sensitivity and mixed signal simulations.