As transistor dimensions continue to shrink, reliability is one of the most significant remaining concerns for CMOS technology [1]. Negative bias temperature instability (NBTI) is one of the dominant ageing mechanisms, in which the threshold voltage (V th ) of a PMOS transistor [2]- [4] increases over time.
The NBTI effect on CMOS memory devices such as SRAM cache has received much attention [5]- [7]. NBTI leads to degradation of the SRAM static noise margin (SNM) due to time-dependent mismatches [8], [9]. One of the practical solutions is periodically flipping each cell to balance the degradation rate [7], [10]. However, since the storage value is considered unpredictable in these works, the performance benefits of this technique are not actually proven.
Our work presents a method to evaluate NBTI lifetime in instruction caches. The contributions are as follows: 1) a novel analysis of the instruction cache that shows the NBTI stress duty cycles for each cache line generally have similar patterns even when running very different programs; 2) an algorithm of running SPICE simulation to predict the NBTI lifetime for the instruction cache based on this observation; 3) lifetime extension of cell flipping in instruction caches is proven by using the stress patterns and lifetime evaluation algorithm.
This paper is organized as follows. Section II presents the theory and simulation results of NBTI on both a single transis-tor and an SRAM cell. In Section III, we demonstrate that the pattern of NBTI stress locality does not vary much between different programs and from this cell lifetimes are calculated. The lifetime evaluation algorithm and the simulation results for instruction caches in ARM and MIPS architectures are presented in Section IV, while Section V describes the lifetime extension by cell flipping. Finally, the paper is concluded in Section VI.
A. Impact of NBTI on Single PMOS Transistor NBTI can result in an increased V th over time. A PMOS transistor can be switched between the NBTI stress phase and the recovery phase. Si-H bonds are disassociated under negative bias condition (V gs = V DD ) and hydrogen spaces and traps are produced at the oxide interface. These hydrogen spaces then diffuse away. Once the stress is removed (V gs = 0), some bonds recover because of recombination with hydrogen. Some traps still remain and therefore the recovery is partial.
Thus, the V th shift is proportional to the density of traps at the oxide interface [4], [11]. The traps are produced during the stress phase and some will be neutralized in the recovery phase. Therefore, V th degradation is highly dependent on the stress duty cycle, which is the probability of a logic zero at the gate of a PMOS transistor in a digital circuit.
In [12], the authors propose a long-term NBTI model to quantify V th degradation after a given operation time t:
where
where ↵ is the key parameter -the stress duty cycle. K v is a function of supply voltage, temperature and technology while T clk is the equivalent stress-recovery period. n is either 1/4 or 1/6 depending on the diffusion spaces (H or H 2 ).
C is the diffusion speed in the gate material. ⇠ 1 and ⇠ 2 represent the annealing probabilities in the oxide and the gate respectively. Finally, t e is the effective oxide thickness indicating the diffusion distance in the oxide and is less than or equal to the oxide thickness, t ox . Based on the long-term NBTI model, above, and data from [12], V th shifts are simulated using MATLAB as in Figure 1. The technology parameters are from the Synopsys 90-nm SPICE model. 90-nm technology is, truly, outdated. However, according to the NBTI models proposed already [2], [3], we believe the trends also apply to smaller technologies.
Figure 2 shows a basic 6-T SRAM cell, in which only the pull-up transistors, MP1 and MP2, would suffer from NBTI [8]. Since MP1 and MP2 are part of cross coupled inverters, only one would be under NBTI stress at any time. This might result in unbalanced V th degradations of these two transistors and thereby lead to a mismatch. The static noise margin (SNM) is the biggest noise voltage the SRAM cell can tolerate. V th mismatch on an SRAM cell can result in an asymmetric transfer characteristic and thereby reduce the SNM, Figure 3.
Using the long-term NBTI model in Equation ( 1) to modify the SPICE model, the degradation in the SRAM cell can be simulated, Figure 4. A cell with 50% stress duty cycle ages most slowly because MP1 and MP2 are matched. Uneven stress accelerates ageing.
The observation is noticed that the data stored in a cache shows very similar patterns when executing different benchmark programs. We ran a test on the instruction caches of ARM and MIPS architectures, using GEM5. 16 benchmark programs, all with more than ten thousand instructions, were chosen. The signal probability of each bit of each cache word is shown in Figure 5. It can be seen that some bits preserve the same values in most locations, consequently leading to NBTI stress locality.
This phenomenon can be explained as following. For any program, we can expect some types of instruction to be used more frequently than the others. Take the ARM processor results in Figure 5a as an example. The most significant four bits are the condition field and "1110" is used for unconditional instructions. The number of unconditional instructions is much bigger than that of conditional ones in any program. As a result, the most significant four bits have a high probability of being "1110" as seen in Figure 5a.
If the SNM degrades to a value smaller than expected noise, the storage data might be flipped, which causes a failure when the data is read out. This gives the NBTI lifetime of the instruction cache. 50% signal probability will give the longest lifetime because both inverters in the SRAM cell age at the same rate and so are not mismatched. The bit with the probability furthest from 50% would fail first, which determines the lifetime of the whole SRAM array.
According to the stress locality in last section, NBTI lifetime of a instruction cache is predictable. We propose Algorithm1 to evaluate the lifetime. This algorithm uses Monte goto Monte Carlo
To model typical operation, the storage value in each cell is set to both 1 and 0 but with different probabilities: we assume NBTI stress duty cycles are distributed with normal distributions with the means and standard deviations shown in Figure 5. For each bit, we run 1600 simulations to guarantee a 95% confidence level within 1% probability error. simulation results predict 6 and 7 years NBTI lifetimes for ARM and MIPS architectures respectively, at which point, the stored values in some SRAM cells start to be corrupted, Figure 6. The motivation for previous cell flipping work, [7], [10], is to avoid a cell holding the same value for a long time. However, since the storage value is considered unpredictable in that work, the performance benefits of periodical cell flipping are not actually proven. On the other hand, in our work, we note that the NBTI stress in the instruction cache stays constant over time.
Figure 7 shows the new probability mean values and standard deviations if cell flipping is applied. By definition, the mean values of the probabilities are at 50%. From this, the new predicted lifetimes can be calculated, as shown in Figure 8. As can be seen, for the same operating conditions, data failures start to occur after more than 300 years in both ARM and MIPS processors. While the exact figure is, of course, dependent on the modelling, it is unarguable that a significant extension to the lifetime of an SRAM instruction cache is achievable by simply flipping cell values periodically.
Rapid shrinkage of CMOS transistors has led to concerns about reliability risks such as ageing. The effect of NBTI on the Static Noise Margin of SRAM-based instruction cache is discussed in this paper. NBTI directly affects the