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  <front>
    <journal-meta />
    <article-meta>
      <title-group>
        <article-title>Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <string-name>Dimitrios Rodopoulos⇤</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Philippe Roussel</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Francky Catthoor</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Yannakis Sazeides</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Dimitrios Soudris⇤ ⇤ MicroLab-ECE-NTUA</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Greece</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>ESAT-KU Leuven</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Belgium</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Belgium</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>⌅ Group-UCY</string-name>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Cyprus Contact Email: drodo@microlab.ntua.gr</string-name>
        </contrib>
      </contrib-group>
      <fpage>10</fpage>
      <lpage>10</lpage>
      <abstract>
        <p>-The delay distribution of a digital circuit path is crucial for the early reliability evaluation of a digital design. As transistors are shrunk to unprecedented dimensions, accurate yet fast estimation of such distributions remains a valid goal. Such distributions may not be provided or are delivered in a heavily abstracted fashion to designers, which reduces the insight into design dependability. In view of the above observations, we propose a technique that approximates the probability density function of a path of digital circuits by exending a well-known computational kernel, namely the Most Probable Failure Point (MPFP) technique. The output of this concept is the failure probability of standard cells or paths thereof for various target delays. We reformulate MPFP and establish a concise methodology for delay distribution approximation. We present simulations for an inverter and outline projections for more complex gates.</p>
      </abstract>
    </article-meta>
  </front>
  <body>
    <sec id="sec-1">
      <title>I. INTRODUCTION</title>
    </sec>
    <sec id="sec-2">
      <title>The inherent time-zero and time-dependent variability of</title>
      <p>
        semiconductor structures creates challenges for the
efficient/accurate modeling of integrated circuit reliability [
        <xref ref-type="bibr" rid="ref1">1</xref>
        ].
      </p>
    </sec>
    <sec id="sec-3">
      <title>Statistical Static Timing Analysis (SSTA) has been prevalent</title>
      <p>
        in handling delay distributions of standard cells. This is split
mainly between depth-first (or path based) [
        <xref ref-type="bibr" rid="ref3">3</xref>
        ], [
        <xref ref-type="bibr" rid="ref4">4</xref>
        ] and
breadthfirst (or block based) [
        <xref ref-type="bibr" rid="ref2">2</xref>
        ], [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ], [
        <xref ref-type="bibr" rid="ref6">6</xref>
        ] techniques.
      </p>
      <p>
        Regardless of SSTA techniques, what is really interesting is
the derivation of the primitive delay distributions of standard
cells. Accurate derivation requires a large number of
simulations or measurements, since rare delay events need to be
accounted for. In many cases, complete distributions are not
even available and only an approximated view of standard
cell delay variability is provided, as in the case of the
stagebased on-chip variation (OCV) [
        <xref ref-type="bibr" rid="ref7">7</xref>
        ]. In view of the above, it
is important to provide an accurate and efficient technique for
the approximation of a standard cell’s delay distribution.
      </p>
      <p>
        The current paper delivers the distribution of an inverter
delay, based on the distributions of the involved threshold
voltages (Vth). The numerical kernel used is an extension of
the Most Probable Failure Point (MPFP), which has been used
for memory cells [
        <xref ref-type="bibr" rid="ref8">8</xref>
        ], [
        <xref ref-type="bibr" rid="ref9">9</xref>
        ], [
        <xref ref-type="bibr" rid="ref10">10</xref>
        ]. We reformulate it using the 2
distribution and use it iteratively to get the probability mass
for various inverter target delays. Project and extensions are
provided for more complex standard cells and paths.
      </p>
    </sec>
    <sec id="sec-4">
      <title>Section II presents general formulation and aspects of prior</title>
      <p>art. Simulation results are analytically presented for the case
of a simple inverter in Section III. In Sections IV and V,
we outline the extensions of our the scheme to more complex
gates and paths. Conclusions are summarized in Section VI.</p>
    </sec>
    <sec id="sec-5">
      <title>II. GENERAL FORMULATION &amp; PRIOR ART</title>
      <p>
        The manifestation of variability in a circuit can be
encapsulated in a vector x (e.g. threshold voltage shift per involved
transistor). A performance metric (e.g. delay of cell) y can
be evaluated at each x point as y(x). A failure occurs when
the performance metric is larger than a specified target (Y ),
namely y &gt; Y . For a specific Y , the MPFP methodology
aims to find the failure, i.e. Pfail(Y ) = P (y &gt; Y ). In order to
connect variability with the failure specification, it is important
to isolate all the values of x that satisfy the failure criterion. If
we use F to represent the set of x values that lead to a failurem
then the failure probability is P (x 2 F ). The challenge posed
is both isolating F and calculating P (x 2 F ) in a systematic
way. We illustrate this situation with an inverter, which has
been profiled using Synopsys NanoTime [
        <xref ref-type="bibr" rid="ref11">11</xref>
        ] according to
Figure 1a. Simulation results have been fitted with MATLAB
for simplicity, as shown in Figure 1b, where a level set is
annotated for a specific Y (roughly 17.5 ps). For all the
simulations presented herein, we have used a publicly available
high performance 16 nm modelcard [
        <xref ref-type="bibr" rid="ref12">12</xref>
        ].
      </p>
      <p>
        According to MPFP, the functionality criterion (which in our
case is y &gt; Y ) is combined with a product of probabilities to
approximate space F [
        <xref ref-type="bibr" rid="ref8">8</xref>
        ], [
        <xref ref-type="bibr" rid="ref9">9</xref>
        ], [
        <xref ref-type="bibr" rid="ref10">10</xref>
        ] and its probability mass,
according to Equation 1 has been used to approximate F . If we
cast the product of probabilities to the delay space (Figure 1c),
it is clear that even if the functionality criterion is correct, the
probability mass of set F is not totally covered. To address
the above inaccuracy, we propose Pfail(Y ) calculation in two
separate steps, described in Subsections III-A and III-B. There
exactly lies the novelty of the current paper, in replacing the
traditional MPFP formulation with the 2 distribution.
(1)
(N 1
      </p>
      <p>Y
i=0
xi)
)
Pfail = max</p>
      <p>P (| Vth,i|
such that y(x) &gt; Y</p>
    </sec>
    <sec id="sec-6">
      <title>III. ADAPTING THE MPFP – INVERTER FOCUS</title>
      <sec id="sec-6-1">
        <title>A. Minimum Identification</title>
        <sec id="sec-6-1-1">
          <title>We isolate the point xA which leads to minimum delay</title>
          <p>ymin. To achieve this, we solve the optimization problem
min {y(x)} for x and also get the distance of xA, which
we notate as rA. For the case of the inverter, it is reasonable
to expect a unique solution to this optimization problem.
This statement has been verified with a series of Synopsys
−0.−50.5 −0.4 −0.3 −0.2 −0.1 ∆ Vth,n (V) 0.1
0
0.2
0.3
0.4
(a) Inverter delay as measured by NanoTime
(d) F approximation using a hypersphere around the local minimum of inverter
delay; additional probability mass is included and the 2 distribution applies</p>
        </sec>
      </sec>
    </sec>
    <sec id="sec-7">
      <title>NanoTime [11] simulations (Figure 1a) and remains valid</title>
      <p>when we use a fitted expression for y(x) as in Figure 1b.</p>
      <sec id="sec-7-1">
        <title>B. Moving away from the Minimum</title>
      </sec>
    </sec>
    <sec id="sec-8">
      <title>The procedure followed in this step is outlined in Figure 1d.</title>
      <sec id="sec-8-1">
        <title>First, we isolate a direction away from xA along which the</title>
        <p>increase of delay is maximum. Having selected a target delay</p>
      </sec>
      <sec id="sec-8-2">
        <title>Y , we move along the above direction, until we reach xY ,</title>
        <p>where y(x) = Y at a distance equal to rY from the point
xA. At this point, the generalized non-central Chi distribution
can be used ( 2). This provides the probability mass of a
hypersphere in the threshold voltage shift space, which is
centered at xA and has a radius equal to rY . By comparing
Figures 1b and 1d, it is clear that the use of the 2 distribution
is rather pessimistic, since x points that are faster than the
target Y are included in space F . However, this is preferable
than the formulation of Equation 1, which is highly optimistic,
since it ignores a huge portion of probability mass, as we
can verify from Figure 1c. On the contrary, the 2-based
)
−9.5 (s
y
a
−10 lreD</p>
        <p>e
−10.5 tr
e
v
−11 fIno0
0.5 −11.5 lgo1</p>
        <p>)
−9.5 (s
y
a
−10 lreD</p>
        <p>e
−10.5 tr
e
v
−11 fIno0
0.5 −11.5 lgo1</p>
        <p>)
−9.5 (s
y
a
−10 lreD</p>
        <p>e
−10.5 tr
e
v
−11 Ifno0
0.5 −11.5 lgo1</p>
        <p>)
−9.5 (s
y
a
−10 lreD</p>
        <p>e
−10.5 tr
e
v
−11 fIno0
0.5 −11.5 lgo1
formulation is guaranteed to contain all the failure points,
provided that point xY is selected based on a greatest ascent,
moving away from xA. This ensures that the “pass” region
only contains “pass” points, even though some are excluded
(pessimism). It is important to note that the above statement
is correct regardless of the shape of y(x), as long as no other
minima exist beyond the level set.</p>
      </sec>
    </sec>
    <sec id="sec-9">
      <title>The goal is to calculate the probability mass of random</title>
      <p>
        variable z2, as defined in Equation 2, where N is the number
of involved transistors (2 in the case of the inverter) and i
is the standard deviation of the Vth per involved transistor.
In the current paper, we assume that all transistors exhibit
the same i. The non-centrality parameter of the utilized
distribution is calculated according to Equation 2 [
        <xref ref-type="bibr" rid="ref13">13</xref>
        ]. Apart
from the involved i, this parameter considers the distance
between point xA and the origin of the axis of the x space,
which is encapsulated as the translated mean Vth shift per
transistor (i.e. µi). For the rest of current paper, we assume
that these mean values are constant. In case transistor aging
is assumed, actual mean Vth shifts become non-zero [
        <xref ref-type="bibr" rid="ref14">14</xref>
        ] and
distance to xA can be easily recalculated.
      </p>
      <p>z2 =
i=0
NX1 xi22 and
i
= NX1 µi22</p>
      <p>i
i=0
(2)</p>
      <p>
        At this point, we note that the approximation of the
mutlivariate distribution for the x vector can be improved by
utilizing distribution transformations, as advised in prior art
[
        <xref ref-type="bibr" rid="ref15">15</xref>
        ]. In the current paper and for the sake of simplicity, we
assume no correlations between involved xi’s, hence we solely
rely on the 2 distribution. With the above approach, we end
up with the Pfail results of Figure 2a. As expected, a higher
for Vth leads to higher Pfail for the same target Y . Finally
it is clear that, in case f (x) has a single maximum (instead
of minimum), we can alternatively start from its maximum
and directly bound set F , instead of its complement. Choice
between minimum/maximum depends on the shape of f (x).
      </p>
      <sec id="sec-9-1">
        <title>C. Getting Delay Distribution Points</title>
      </sec>
    </sec>
    <sec id="sec-10">
      <title>The failure probability for a target Y satisfies Equation 3,</title>
      <p>where PDFy and CDFy are the probability and cumulative
density functions for y (inverter delay in our case).
Z Y
Pfail = P (y &gt; Y ) = 1</p>
      <p>CDFy (Y ) = 1</p>
      <sec id="sec-10-1">
        <title>PDFy dy (3)</title>
        <p>1</p>
      </sec>
    </sec>
    <sec id="sec-11">
      <title>It is clear that by repeating the process of Subsection III-B</title>
      <p>for different values of Y we can isolate the cumulative
probability for various delay specifications of the target circuit.</p>
      <sec id="sec-11-1">
        <title>Based on the Pfail vs. Y relation derived in Figure 2a, we easily</title>
        <p>produce the respective CDFy data, as illustrated in Figure 2b.</p>
      </sec>
      <sec id="sec-11-2">
        <title>A simple differentiation yields the corresponding PDFy . This</title>
        <p>effectively constitutes the delay distribution of the inverter.
It is solely based on a NanoTime-compatible description of
the inverter and uses values of the standard deviation for Vth
shifts (multiple values inspected). This being a non-analytical
10Y2 (ps)
102y (ps)
102y (ps)
103
103
103
(a) Inverter failure probability for various values of Vth shift spread
(b) Cumulative density function of inverter delay for various values of
(c) Probability density function of inverter delay for various values of
.)u100
.(
p
s
s
a
.M10−10
b
o
r
P
.
c
a
n10−20
U 0.01 0.02 0.03 0.04 0.05 σ∆ 0V.t0h6(V) 0.07 0.08 0.09
0.1
0.11
(d) Unaccounted probability mass using our approximation
approach, it is important to highlight the probability mass that
is unaccounted for. This corresponds to events that are not
included in the presented PDFy, as in the case of very high
target delays (which can be safely assumed as negligibly rare).</p>
      </sec>
    </sec>
    <sec id="sec-12">
      <title>The unaccounted probability mass is illustrated in Figure 2d.</title>
      <p>
        Evidently, the higher the spread of Vth shifts is, the higher the
unaccounted probability mass is using our technique. However,
when considering values for Vth that are relevant to
current technologies [
        <xref ref-type="bibr" rid="ref14">14</xref>
        ], our technique behaves with
sufficient accuracy. The delay of the inverter is lower bounded
(Figure 1b). This means that delay distribution of the inverter
does not have a tail on the left. However, as increases, the
right-hand tail extends uncontrollably.
      </p>
    </sec>
    <sec id="sec-13">
      <title>IV. GENERALIZING TO COMPLEX GATES</title>
    </sec>
    <sec id="sec-14">
      <title>Standard cells with more than one transistor in the pull-up/</title>
      <p>
        down branches, require a systematic way of identifying the
delay minimum (of maximum). In the general case, one has
no information about y(x), which is evaluated with NanoTime
for each iteration. We implement coordinate descent [
        <xref ref-type="bibr" rid="ref16">16</xref>
        ]
according to Algorithm 1 for the case of a NAND gate.
Algorithm 1: Coordinate descent used in the current paper,
based on iteration limit and Vth step equal to s
      </p>
      <p>}
1 while (itNum&lt;Limit) {
2 for i{2 0, 1, ..., N 1} {
3 s =find descenting direction for xi
4 if y(x0, ..., xi + s, ..., xN 1) &lt;prev_delay
5 {Update x with xi + s}
6 else {Proceed to next transistor}
7
50 100
Iteration Number (p.u.)</p>
      <p>(a)
50 100
Iteration Number (p.u.)
(c)
150
150</p>
      <p>0.2</p>
    </sec>
    <sec id="sec-15">
      <title>Algorithm 1 has been implemented as Perl wrapper around</title>
    </sec>
    <sec id="sec-16">
      <title>NanoTime. We initially sweep the y(x) function for the</title>
    </sec>
    <sec id="sec-17">
      <title>NAND case, in a 100 mV granularity (&gt; 14, 000 NanoTime</title>
      <p>iterations). This is a crude estimation of the minimum value
and the value of the corresponding Vth shifts (i.e. estimation
of xA. Using Algorithm 1, we succeed in identifying the
minimum point in ⇠ 160 NanoTime iterations (Figure 3).</p>
      <p>Given the multitude of transistors in the pull-up/-down
branches of standard cells, multiple minima/maxima may exist
for y(x) (i = 0, 1, ..., M 1). Given the symmetry of such
cells, we may treat only one of these points (xAi) with the
technique of Subsection III-B. The cumulative probability
around xAi can be multiplied by M to provide the total
probability mass of the “pass” event at delay Y . This is,
conceptually, the complement of the F set (“failure” region).</p>
      <sec id="sec-17-1">
        <title>By subtracting from one, we get Pfail, which is substituted</title>
        <p>in Equation 3. Repeating this for different Y values
(Subsection III-C) yields the delay distribution of the standard cell.</p>
      </sec>
    </sec>
    <sec id="sec-18">
      <title>Clearly, in case y(x) has a finite number of maxima (instead</title>
      <p>of minima), a dual approach can be maintained. This leads to
bounding set F , instead of the latter’s complement. The choice
between the two courses of action can be resolved with a
highlevel view of y(x), e.g. by crudely sweeping the x space.</p>
    </sec>
    <sec id="sec-19">
      <title>The techniques of minimum/maximum identification (i.e.</title>
    </sec>
    <sec id="sec-20">
      <title>Subsection III-A and Algorithm 1) and probability mass</title>
      <p>calculation (i.e. Subsection III-B) need to be generalized for
an arbitrary number of transistors (N ) in the standard cell.</p>
    </sec>
    <sec id="sec-21">
      <title>The two step technique of Subsections III-A and III-B should</title>
      <p>account for plateaus in y(x) and non-global minima/maxima.</p>
    </sec>
    <sec id="sec-22">
      <title>All these enhancements constitute points for future work.</title>
    </sec>
    <sec id="sec-23">
      <title>V. GENERALIZING TO STANDARD CELL PATHS</title>
    </sec>
    <sec id="sec-24">
      <title>Given a (sufficiently) accurate PDF approximation for the</title>
      <p>
        delay distribution of a set of standard cells, it is quite easy
to provide the delay distribution for a path of standard cells.
Given that we target the sum of the delays of the involved
standard cells, the respective distribution is produced with
convolution of the delay distributions [
        <xref ref-type="bibr" rid="ref17">17</xref>
        ]. In Figure 4 we
present the results for a chain of four inverters, each one being
identical to the one used in Section III. The chain of operations
is exactly inverted: we convolute PDFy the appropriate amount
of times (four) and produce Figure 4a, namely the delay PDF
for the path of inverters (PDFy4). A simple integration yields
the CDFy4 (Figure 4b) and subtraction from one provides the
failure probability of the simple four-inverter path for various
target delays (Y ), as illustrated in Figure 4c. We note that
the resulting failure probabilities span a wider Y range in
comparison to the single-inverter equivalent. Also, there is a
general transposition of the nominal delay in comparison to
Figure 2a, given the connection of inverters in series.
      </p>
    </sec>
    <sec id="sec-25">
      <title>VI. CONCLUSIONS</title>
    </sec>
    <sec id="sec-26">
      <title>In the current paper we disclose an iterative technique</title>
      <p>used to approximate the delay distribution of a standard cell.
Complete reduction to practice has been achieved for the
case of a simple inverter and extensions are discussed for
more complex gates and paths of standard cells. The proposed
technique starts from the Most Probable Failure Point (MPFP)
concept, which has been traditionally used in prior art for
reliability modeling of memory cells. In the current paper, we
extendMPFP to improve probability mass coverage, using the</p>
      <sec id="sec-26-1">
        <title>2 distribution and coordinate descend.</title>
      </sec>
    </sec>
    <sec id="sec-27">
      <title>ACKNOWLEDGMENTS</title>
    </sec>
    <sec id="sec-28">
      <title>Partial support by European Commission project FP7-612069</title>
    </sec>
    <sec id="sec-29">
      <title>HARPA. Prof. Julius Georgiou (UCY, CY) acknowledged for</title>
    </sec>
    <sec id="sec-30">
      <title>EDA support. Dr. Pieter Weckx (KUL, BE) and Prof. Ramon</title>
    </sec>
    <sec id="sec-31">
      <title>Canal (UPC, ES) acknowledged for inspiring discussions.</title>
      <p>100
100
101
0.08
)
0.06 (VVth
0.04 σ∆</p>
    </sec>
  </body>
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