-In this paper a reliability-aware design method based on the gm/ID-methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. Within this method the whole simulation effort is shifted to a single transistor level. With a generated stochastic Look-Up table the small signal characteristics of transistors and circuits can be predicted. Exemplarily, a reliability-aware design for common source amplifiers is shown and the predicted values are compared to those from a traditional simulation showing good data fitting and small deviations.
Reliable design flows for integrated CMOS circuits must take into account all effects that influence whole circuits or several single transistors. For larger technology nodes it was sufficient to design a circuit with respect to pure electrical properties like voltages, currents or capacitance. However, the progressive downscaling of CMOS transistors necessitates a design flow that is able to consider both process variations and time-dependent degradation at early stages of the design. Other approaches will lead to an iterative simulation flow once an initial design has been found. The drawback of a design flow that depends on intensive simulations at system level is that for example aging simulations on this level are very time consuming or even unfeasible. Therefore a methodology is needed that enables designers to consider all effects on scaled down devices and does not evoke complex simulations at system level.
The two most important aging mechanisms in CMOS transistors are Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) [1]. For both effects exist several different models that can explain some of the observed phenomena linked to these mechanisms. Nevertheless, the physics behind BTI and HCD are yet not fully understood. The main impact of those aging influences is an increase of the charge under the gate oxide of transistors causing higher threshold voltage Vth, higher Rds,on and reduced mobility µn/p. Simply expressed, the transistor becomes slower.
This work is based on the gm/ID-methodology that was firstly introduced by [2]. The main advantage of this design methodology is its capability to consistently describe the behavior of CMOS transistors over all regimes of operation. Thus, designers are able to contrive circuits in which all transistors are operating in moderate inversion. This operating point is the best trade-off between speed and power consumption. However, in this operating region transistors are most badly affected by HCD and BTI which is shown in figure 1.
In order to ensure reliable low power circuits that are Fig. 1. Deviation of threshold voltage Vth due to HCI of NMOS transistors over a period of 3 Ms versus the inversion coefficient IC for different lengths L. resistant towards process variations the well known gm/IDmethodology has to be enhanced [3].
The presented Reliability-AwaRE (RARE) design flow is based on stochastic Look-Up-Tables (LUT) including all necessary variables for the gm/ID-methodology. The LUT contains the distribution functions of these required parameters and their particular behavior over time for 3 Ms (⇡ 10 years). The LUT entries are generated through transient simulations of 2000 P- and NMOS transistors utilizing a modified BSIM6 [4] transistor model presented in [5]. Subsequently, the extracted distributions can be used in a modified gm/ID-design flow and, furthermore, a direct calculation of small signal parameters can be carried out. This new approach shifts the simulation effort from the system to the single-transistor level and realizes a reliability-aware design method for CMOS circuits.
II. THE gm/ID -METHODOLOGY
The main objective of the gm/Id-methodology is describing the operating point of MOS transistors with W/L-independent metrics. In order to achieve this goal the so called transconductance efficiency gm/Id and the inversion coefficient IC are used. Where gm ID = =
TOP = {IC, ID, L} . and
IC =
ID
I0 · (W/L)
(
W =
ID · L I0 · IC .
To improve the accuracy of this method Look-up tables are used because the simulated data considers additional effects which may be included in specific transistor models and manufacturing processes. The transconductance is then derived from gm = ✓ gm ◆
ID sim · ID .
Utilizing this design method the operating point of every transistor in a circuit can be derived and furthermore small signal performances of the circuit can be directly analyzed.
III.
GENERATION OF STOCHASTIC LUTS
Due to the fact that within the mentioned gm/Idmethodology every transistor is designed separately, it is sufficient for the LUT to analyze the behavior of one PMOS and one NMOS transistor. The only parameters that have to be swept, are the length L and the gate-source voltage Vgs.
Lmin 0
L Vgs 3 ⇥ Lmin
Vdd = 1 V
(
Within this work a 65 nm CMOS technology is considered the maximum length of which is confined to 3 ⇥ Lmin. For every specific sweep point a 3 Ms transient simulation with 2000 transistors affected by process and temperature variation is performed. Table I shows the normal distribution functions of all considered parameters with their particular mean value µ and standard deviation . The values for µ and correspond to those which are specified by the technology.
Fig. 2. Test benches for NMOS (a) and PMOS (b) transistors.
The simulation data is fitted either with a normal fn(x, t) (7) or with a log-normal fln(x, t) (8) distribution depending on which one describes the basic population best. Two different distribution functions are required because some distribution functions are symmetrical and some possibly not. fn(x, t) = p
exp fln(x, t) = < p 2⇡1 x exp 1 2⇡ 8 x denotes any fitted parameter (e.g. IC, gm) and t is the time. These two functions were chosen because both have two fitting parameters (µ, ) with the same meaning and this simplifies the calculus of small signal parameters. The time dependency comes in with the fitting of µ and , as a matter of simplicity, with a fourth order polynomial function over time which gives µ(t) = p1,µt4 + p2,µt3 + p3,µt2 + p4,µt + p5,µ and (t) = p1, t4 + p2, t3 + p3, t2 + p4, t + p5, . (7) (8) (9) (10)
The numerical analysis is performed in MATLAB. The simulation data is reduced from 16 GB to approximately 240 MB containing the same amount of information. The data reduction can be realized by storing the coefficient of distribution and fitting functions instead of storing the whole data. The second advantage is that this simulation has to be performed only once for every technology. Moreover, the resulting time-dependent distribution functions for the parameters can subsequently be used in the gm/Id-methodology which is shown in the next section.
IV.
CALCULATION OF SMALL SIGNAL PARAMETERS
In order to perform the calculation of small signal
parameters for MOS transistors as well as circuit performances like the
DC gain ADC of common source amplifiers, some calculation
specification has to be performed in a different manner because
random variables are considered. The inversion coefficient IC
is given by equation (
Therefore, let fz (z) = z = x y , gm/ID = gm ID then the problem is solved for x distribution is given by = z · y. The resulting Z1
2⇡ 0 ✓ (yz)2 2 x x y y p
1 2rzy2 x y r2 + exp 2(1 1
r2) · ... y2 2 + h(y, z) y ◆ dy .
(14) The function h(y, z) contains all terms considering the mean values of the two distributions and r = cov(x,y)/ x y. Equation (14) applies for both the calculation of I C and gm/ID because the change in ID is correlated to I0 and gm is correlated to ID. All calculated distributions are time-dependent because µi and i are. Therefore the correlation coefficient r is also timedependent and lim rij = rij,0 t!1 holds, because all aging effects will saturate at a certain point in time and then the distribution parameters will become timeindependent. This is due to the fact that every operating point has a certain maximum amount of traps that can be generated and occupied. The mentioned time dependency necessitates a repeated evaluation of these parameters for several different time steps.
With the calculation of these distributions the LUT contains all necessary entries for each sweep point to be used within the gm/ID-method. Figures 3, 4 and 5 show exemplarily the distribution of gm, ID as well as gm/ID. The distribution of (13) (15) gm/ID shows a unique behavior over time because gm and ID are unequally affected by aging and this leads to a compression of the gm/ID distribution.
Subsequently, the DC gain ADC of the CS-Amp is derived with the small signal characteristics of the particular M3
Ibias M1 VSS MOSFETs. The calculated distribution function of ADC is compared to the distribution of simulated results for the CSAmp in CADENCE VIRTUOSO. Table III shows the chosen value for the three transistors.
APPROPRIATE OPERATING POINT PARAMETER VALUES FOR
TRANSISTORS IN THE CS-AMP Parameter
W1 W2 W3 L1 L2 L3
Parameter
IC1 IC2 IC3 ID I0 100 µA 995 nA
As it can be seen, the amplifier is designed in a way that M 1 operates in moderate inversion and the two transistors forming the current mirror operate in strong inversion.
The DC gain can be approximated by ADC = ⇣ gds,1 ⌘
ID ⇣ gm,1 ⌘
ID sim
sim + ⇣ gIdDs,2 ⌘ sim =
gm,1 . (16)
The calculation of ADC follows the same scheme like that for I C and gm/ID. All conductances are time-dependent, therefore the expression for ADC already includes the impact of aging and process/environmental variations. Moreover, it is possible to evaluate which is the most crucial parameter for both effects at this very early design stage. Table IV shows a comparison of predicted fresh/aged ADC and those values simulated in CADENCE. The initial amplification as well as the impact due to aging is overestimated because the prediction neglects the load resistance.
COMPARISON OF MEAN PREDICTED AND SIMULATED
FRESH/AGED ADC .
Fresh ADC,pre ADC,sim
Value 93.1 dB 82.3 dB
Aged ADC,pre ADC,sim
Value 13.7 dB 19.12 dB
Figures 7 and 8 show the distribution for the simulated gm,1 as well as the relative error between the simulated and calculated distribution. Around the mean value µgm,1 = 1 mS the relative error is less than 3%. For lower and higher values the error increases, but in order to fit this region another distribution from the LUT has to be utilized. ADC cannot be plotted because it is a 5-dimensional function. Therefore, only the error for gm,1 is shown, but the shown deviation applies also for gds,1 and gds,2.
Additionally, the shown calculation can be carried out for every small signal circuit performance.
VI.
In this paper a design method is presented that allows designers to consider process as well as environmental variations and aging effect at early design stages. Moreover, the method shifts the simulation effort to a single transistor level by generating a stochastic Look-Up Table. This leads to reduced simulation time and amount of data that must be stored. With this data good predictions for small signal parameters of MOSFET and circuit performances can be derived. The method is evaluated with the design of a common source amplifier showing only small errors in the prediction of the initial distribution as well as for the degraded distribution.