Reliable design flows for integrated CMOS circuits must take into account all effects that influence whole circuits or several single transistors. For larger technology nodes it was sufficient to design a circuit with respect to pure electrical properties like voltages, currents or capacitance. However, the progressive downscaling of CMOS transistors necessitates a design flow that is able to consider both process variations and time-dependent degradation at early stages of the design. Other approaches will lead to an iterative simulation flow once an initial design has been found. The drawback of a design flow that depends on intensive simulations at system level is that for example aging simulations on this level are very time consuming or even unfeasible. Therefore a methodology is needed that enables designers to consider all effects on scaled down devices and does not evoke complex simulations at system level.
The two most important aging mechanisms in CMOS transistors are Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) [1]. For both effects exist several different models that can explain some of the observed phenomena linked to these mechanisms. Nevertheless, the physics behind BTI and HCD are yet not fully understood. The main impact of those aging influences is an increase of the charge under the gate oxide of transistors causing higher threshold voltage V th , higher R ds,on and reduced mobility µ n/p . Simply expressed, the transistor becomes slower. This work is based on the gm /I D -methodology that was firstly introduced by [2]. The main advantage of this design methodology is its capability to consistently describe the behavior of CMOS transistors over all regimes of operation. Thus, designers are able to contrive circuits in which all transistors are operating in moderate inversion. This operating point is the best trade-off between speed and power consumption. However, in this operating region transistors are most badly affected by HCD and BTI which is shown in figure 1.
In order to ensure reliable low power circuits that are resistant towards process variations the well known gm /I Dmethodology has to be enhanced [3].
The presented Reliability-AwaRE (RARE) design flow is based on stochastic Look-Up-Tables (LUT) including all necessary variables for the gm /I D -methodology. The LUT contains the distribution functions of these required parameters and their particular behavior over time for 3 Ms (⇡ 10 years). The LUT entries are generated through transient simulations of 2000 P-and NMOS transistors utilizing a modified BSIM6 [4] transistor model presented in [5]. Subsequently, the extracted distributions can be used in a modified gm /I D -design flow and, furthermore, a direct calculation of small signal parameters can be carried out. This new approach shifts the simulation effort from the system to the single-transistor level and realizes a reliability-aware design method for CMOS circuits.
The main objective of the gm /Id-methodology is describing the operating point of MOS transistors with W /L-independent metrics. In order to achieve this goal the so called transconductance efficiency gm /Id and the inversion coefficient IC are used. Where
and
with I 0 = 2nµC ox V 2 t being a technology specific current. Due to the fact that I D / W /L both metrics are W /Lindependent. Thus, the operating point of any MOS transistor can be described by the tuple
By choosing an operating point, e.g. in moderate inversion, the IC is set, which leads to I D , further L should be chosen large enough to prevent short channel effects. According to equation (2) the width can be calculated as
To improve the accuracy of this method Look-up tables are used because the simulated data considers additional effects which may be included in specific transistor models and manufacturing processes. The transconductance is then derived from
Utilizing this design method the operating point of every transistor in a circuit can be derived and furthermore small signal performances of the circuit can be directly analyzed.
Due to the fact that within the mentioned gm /Idmethodology every transistor is designed separately, it is sufficient for the LUT to analyze the behavior of one PMOS and one NMOS transistor. The only parameters that have to be swept, are the length L and the gate-source voltage V gs .
Within this work a 65 nm CMOS technology is considered the maximum length of which is confined to 3 ⇥ L min . For every specific sweep point a 3 Ms transient simulation with 2000 transistors affected by process and temperature variation is performed. Table I shows the normal distribution functions of all considered parameters with their particular mean value µ and standard deviation . The values for µ and correspond to those which are specified by the technology. The simulation data is fitted either with a normal f n (x, t) (7) or with a log-normal f ln (x, t) (8) distribution depending on which one describes the basic population best. Two different distribution functions are required because some distribution functions are symmetrical and some possibly not.
x denotes any fitted parameter (e.g. IC, g m ) and t is the time. These two functions were chosen because both have two fitting parameters (µ, ) with the same meaning and this simplifies the calculus of small signal parameters. The time dependency comes in with the fitting of µ and , as a matter of simplicity, with a fourth order polynomial function over time which gives
and
The numerical analysis is performed in MATLAB. The simulation data is reduced from 16 GB to approximately 240 MB containing the same amount of information. The data reduction can be realized by storing the coefficient of distribution and fitting functions instead of storing the whole data. The second advantage is that this simulation has to be performed only once for every technology. Moreover, the resulting time-dependent distribution functions for the parameters can subsequently be used in the gm /Id-methodology which is shown in the next section.
In order to perform the calculation of small signal parameters for MOS transistors as well as circuit performances like the DC gain A DC of common source amplifiers, some calculation specification has to be performed in a different manner because random variables are considered. The inversion coefficient IC is given by equation ( 2) where I D , I 0 , W and L are partially independent random variables denoted with bold print. An important fact is that some parameters are not stochastically independent, thus the covariance is cov(x, y) 6 = 0 .
(11)
In common design flows the technology current I 0 is treated as a constant value for each technology. However, in this case this current is given by I 0 = 2nµC ox V t 2 which is not a constant value because each parameter is affected in a different way by the variations specified in table I. Table II shows the interdependencies of I 0 and the process/environmental variations. For the technology current follows
where
holds, because all aging effects will saturate at a certain point in time and then the distribution parameters will become timeindependent. This is due to the fact that every operating point has a certain maximum amount of traps that can be generated and occupied. The mentioned time dependency necessitates a repeated evaluation of these parameters for several different time steps.
With the calculation of these distributions the LUT contains all necessary entries for each sweep point to be used within the gm /I D -method.
In this section a common source amplifier (CS-Amp) which is shown in figure 6 is designed with the gm /I D -method. Subsequently, the DC gain A DC of the CS-Amp is derived with the small signal characteristics of the particular
Fig. 6. Common source amplifier with active PMOS current mirror load.
MOSFETs. The calculated distribution function of A DC is compared to the distribution of simulated results for the CS-Amp in CADENCE VIRTUOSO. Table III shows the chosen value for the three transistors. As it can be seen, the amplifier is designed in a way that M 1 operates in moderate inversion and the two transistors forming the current mirror operate in strong inversion.
The DC gain can be approximated by
The calculation of A DC follows the same scheme like that for IC and gm /I D . All conductances are time-dependent, therefore the expression for A DC already includes the impact of aging and process/environmental variations. Moreover, it is possible to evaluate which is the most crucial parameter for both effects at this very early design stage. Table IV shows a comparison of predicted fresh/aged A DC and those values simulated in CADENCE. The initial amplification as well as the impact due to aging is overestimated because the prediction neglects the load resistance. as well as the relative error between the simulated and calculated distribution. Around the mean value µ gm,1 = 1 mS the relative error is less than 3%. For lower and higher values the error increases, but in order to fit this region another distribution from the LUT has to be utilized. A DC cannot be plotted because it is a 5-dimensional function. Therefore, only the error for g m,1 is shown, but the shown deviation applies also for g ds,1 and g ds,2 .
Additionally, the shown calculation can be carried out for every small signal circuit performance.
In this paper a design method is presented that allows designers to consider process as well as environmental variations and aging effect at early design stages. Moreover, the method shifts the simulation effort to a single transistor level by generating a stochastic Look-Up Table. This leads to reduced simulation time and amount of data that must be stored. With this data good predictions for small signal parameters of MOSFET and circuit performances can be derived. The method is evaluated with the design of a common source amplifier showing only small errors in the prediction of the initial distribution as well as for the degraded distribution.