17 Reliability-Aware Design Method for CMOS Circuits Theodor Hillebrand, Nico Hellwege, Steffen Paul, Dagmar Peters-Drolshagen Institute of Electrodynamics and Microelectronic (ITEM.me) University of Bremen, Germany, +49(0)421/218-62551 {hillebrand, hellwege, steffen.paul, peters}@me.uni-bremen.de Abstract—In this paper a reliability-aware design method based on the gm/ID -methodology is presented which allows designers of integrated analog circuits to consider process as well as environmental variations and aging effects already at early design stages. Within this method the whole simulation effort is shifted to a single transistor level. With a generated stochastic Look-Up table the small signal characteristics of transistors and circuits can be predicted. Exemplarily, a reliability-aware design for common source amplifiers is shown and the predicted values are compared to those from a traditional simulation showing good data fitting and small deviations. Fig. 1. Deviation of threshold voltage Vth due to HCI of NMOS transistors I. I NTRODUCTION over a period of 3 Ms versus the inversion coefficient IC for different lengths L. Reliable design flows for integrated CMOS circuits must take into account all effects that influence whole circuits or several single transistors. For larger technology nodes it was resistant towards process variations the well known gm/ID - sufficient to design a circuit with respect to pure electrical methodology has to be enhanced [3]. properties like voltages, currents or capacitance. However, the The presented Reliability-AwaRE (RARE) design flow progressive downscaling of CMOS transistors necessitates a is based on stochastic Look-Up-Tables (LUT) including all design flow that is able to consider both process variations necessary variables for the gm/ID -methodology. The LUT and time-dependent degradation at early stages of the design. contains the distribution functions of these required parameters Other approaches will lead to an iterative simulation flow once and their particular behavior over time for 3 Ms (⇡ 10 years). an initial design has been found. The drawback of a design The LUT entries are generated through transient simulations of flow that depends on intensive simulations at system level 2000 P- and NMOS transistors utilizing a modified BSIM6 [4] is that for example aging simulations on this level are very transistor model presented in [5]. Subsequently, the extracted time consuming or even unfeasible. Therefore a methodology distributions can be used in a modified gm/ID -design flow and, is needed that enables designers to consider all effects on furthermore, a direct calculation of small signal parameters can scaled down devices and does not evoke complex simulations be carried out. This new approach shifts the simulation effort at system level. from the system to the single-transistor level and realizes a The two most important aging mechanisms in CMOS tran- reliability-aware design method for CMOS circuits. sistors are Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) [1]. For both effects exist several different II. T HE gm/ID -M ETHODOLOGY models that can explain some of the observed phenomena The main objective of the gm/Id-methodology is describing linked to these mechanisms. Nevertheless, the physics behind the operating point of MOS transistors with W/L-independent BTI and HCD are yet not fully understood. The main impact metrics. In order to achieve this goal the so called transcon- of those aging influences is an increase of the charge under the ductance efficiency gm/Id and the inversion coefficient IC are gate oxide of transistors causing higher threshold voltage Vth , used. Where higher Rds,on and reduced mobility µn/p . Simply expressed, ⇣ ⌘ the transistor becomes slower. gm 1 @ID @ ln(ID ) @ ln WID /L = = = (1) This work is based on the gm/ID -methodology that was ID ID @VGS @VGS @VGS firstly introduced by [2]. The main advantage of this design and methodology is its capability to consistently describe the ID behavior of CMOS transistors over all regimes of operation. IC = (2) I0 · (W/L) Thus, designers are able to contrive circuits in which all transistors are operating in moderate inversion. This operating with I0 = 2nµCox Vt2 being a technology specific current. point is the best trade-off between speed and power consump- Due to the fact that ID / W/L both metrics are W/L- tion. However, in this operating region transistors are most independent. Thus, the operating point of any MOS transistor badly affected by HCD and BTI which is shown in figure 1. can be described by the tuple In order to ensure reliable low power circuits that are TOP = {IC, ID , L} . (3) Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors. 18 By choosing an operating point, e.g. in moderate inversion, the The simulation data is fitted either with a normal fn (x, t) IC is set, which leads to ID , further L should be chosen large (7) or with a log-normal fln (x, t) (8) distribution depending on enough to prevent short channel effects. According to equation which one describes the basic population best. Two different (2) the width can be calculated as distribution functions are required because some distribution ID · L functions are symmetrical and some possibly not. W = . (4) I0 · IC ✓ ◆2 ! 1 1 x µ To improve the accuracy of this method Look-up tables are fn (x, t) = p exp (7) 2⇡ 2 used because the simulated data considers additional effects ✓ which may be included in specific transistor models and 8 ⇣ ⌘2 ◆ < p 1 exp 1 ln (x) µ x>0 manufacturing processes. The transconductance is then derived fln (x, t) = 2⇡ x 2 (8) from : ✓ ◆ 0 x0 gm gm = · ID . (5) ID sim x denotes any fitted parameter (e.g. IC, gm ) and t is the time. These two functions were chosen because both have two fitting Utilizing this design method the operating point of every parameters (µ, ) with the same meaning and this simplifies transistor in a circuit can be derived and furthermore small the calculus of small signal parameters. The time dependency signal performances of the circuit can be directly analyzed. comes in with the fitting of µ and , as a matter of simplicity, with a fourth order polynomial function over time which gives III. G ENERATION OF STOCHASTIC LUT S µ(t) = p1,µ t4 + p2,µ t3 + p3,µ t2 + p4,µ t + p5,µ (9) Due to the fact that within the mentioned gm/Id- methodology every transistor is designed separately, it is and sufficient for the LUT to analyze the behavior of one PMOS and one NMOS transistor. The only parameters that have to be swept, are the length L and the gate-source voltage Vgs . (t) = p1, t4 + p2, t3 + p3, t2 + p4, t + p5, . (10) Lmin  L  3 ⇥ Lmin 0  Vgs  Vdd = 1 V (6) The numerical analysis is performed in M ATLAB. The sim- ulation data is reduced from 16 GB to approximately 240 MB containing the same amount of information. The data reduction Within this work a 65 nm CMOS technology is considered can be realized by storing the coefficient of distribution and the maximum length of which is confined to 3 ⇥ Lmin . For fitting functions instead of storing the whole data. The second every specific sweep point a 3 Ms transient simulation with advantage is that this simulation has to be performed only once 2000 transistors affected by process and temperature variation for every technology. Moreover, the resulting time-dependent is performed. Table I shows the normal distribution functions distribution functions for the parameters can subsequently be of all considered parameters with their particular mean value used in the gm/Id-methodology which is shown in the next µ and standard deviation . The values for µ and correspond section. to those which are specified by the technology. TABLE I. PARAMETERS OF NORMAL DISTRIBUTION FUNCTIONS OF ALL CONSIDERED QUANTITIES IV. C ALCULATION OF SMALL SIGNAL PARAMETERS Parameter Symbol µ p Temperature T 27 C 2 C In order to perform the calculation of small signal parame- Gate oxide thickness tox tox,norm 7 pm Length L Lspec 2 nm ters for MOS transistors as well as circuit performances like the Width W Wspec 2 nm DC gain ADC of common source amplifiers, some calculation Gate doping concentration Ngate Ngate,norm 5 · 1022 m 3 specification has to be performed in a different manner because Channel doping concentration 1 · 1021 m 3 Ndep Ndep,norm random variables are considered. The inversion coefficient IC Source / Drain doping concentration NS/D NS/D,norm 1 · 1023 m 3 is given by equation (2) where ID , I0 , W and L are partially independent random variables denoted with bold print. An Figure 2 shows the test benches for NMOS and PMOS important fact is that some parameters are not stochastically transistors. independent, thus the covariance is cov(x, y) 6= 0 . (11) In common design flows the technology current I0 is treated as a constant value for each technology. However, in this case this current is given by I0 = 2nµCox Vt 2 which is not a constant value because each parameter is affected in a different way by the variations specified in table I. Table II shows the interdependencies of I0 and the process/environmental Fig. 2. Test benches for NMOS (a) and PMOS (b) transistors. variations. Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors. 19 TABLE II. I NTERDEPENDENCIES OF I0 AND THE gm/ID shows a unique behavior over time because g PROCESS / ENVIRONMENTAL VARIATIONS m and ID are unequally affected by aging and this leads to a compression Parameter Main Dependencies n T, Ndep , Ngate , tox of the gm/ID distribution. µ T Cox tox Vt T For the technology current follows ✓ ◆N Y N ✓ ◆ 1 1 I0 =K p · ... 2⇡ i=1 i xi N ✓ ◆2 ! ✓ ◆2 ! 1 X zi µ i 1 zT µT exp · exp 2 i=1 i 2 T (12) where zi = ln xi _ zi = xi depending on whether the variable is log-normal or normal distributed. K contains all constant Fig. 3. Distribution function of transconductance gm of NMOS transistors factors and N is the number of independent random variables. with L = 130 nm and Vgs = 0.75 V over 3 Ms. The correlation coefficients are neglected because rij = 0 for I0 e.g. the change in temperature is uncorrelated to a change in doping concentration and vice versa. The resulting distribution is a normal distribution if all contributing distributions are normal distributions, and it is log-normal distributed if at least one variable follows a log-normal distribution. In order to calculate IC and gm/ID two random variables have to be divided and the resulting distribution must be extracted. Therefore, let x gm z= , gm/ID = (13) y ID then the problem is solved for x = z · y. The resulting distribution is given by Z1  y 1 Fig. 4. Distribution function of drain current ID of NMOS transistors with fz (z) = p exp · ... 2⇡ x y 1 r 2 2(1 r2 ) L = 130 nm and Vgs = 0.75 V over 3 Ms. 0 ✓ ◆ (yz)2 2rzy2 y2 2 + 2 + h(y, z) dy . (14) x x y y The function h(y, z) contains all terms considering the mean values of the two distributions and r = cov(x,y)/ x y . Equation (14) applies for both the calculation of IC and gm/ID because the change in ID is correlated to I0 and gm is correlated to ID . All calculated distributions are time-dependent because µi and i are. Therefore the correlation coefficient r is also time- dependent and lim rij = rij,0 (15) t!1 holds, because all aging effects will saturate at a certain point in time and then the distribution parameters will become time- independent. This is due to the fact that every operating point Fig. 5. Distribution function of the calculated transconductance efficiency gm/ID of NMOS transistors with L = 130 nm and Vgs = 0.75 V over 3 Ms. has a certain maximum amount of traps that can be generated and occupied. The mentioned time dependency necessitates a repeated evaluation of these parameters for several different V. C OMMON S OURCE A MPLIFIER time steps. In this section a common source amplifier (CS-Amp) which With the calculation of these distributions the LUT contains is shown in figure 6 is designed with the gm/ID -method. all necessary entries for each sweep point to be used within the gm/ID -method. Figures 3, 4 and 5 show exemplarily the Subsequently, the DC gain ADC of the CS-Amp is de- distribution of gm , ID as well as gm/ID . The distribution of rived with the small signal characteristics of the particular Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors. 20 VDD VDD M3 M2 Vout Ibias VSS M1 Vin VSS Fig. 7. Distribution function of simulated gm,1 of a common source amplifier Fig. 6. Common source amplifier with active PMOS current mirror load. over 3 Ms. MOSFETs. The calculated distribution function of ADC is compared to the distribution of simulated results for the CS- Amp in C ADENCE V IRTUOSO. Table III shows the chosen value for the three transistors. TABLE III. A PPROPRIATE OPERATING POINT PARAMETER VALUES FOR TRANSISTORS IN THE CS-A MP Parameter Value Parameter Value W1 260 nm IC1 5 W2 260 nm IC2 50 W3 2.6 µm IC3 50 L1 130 nm L2 130 nm ID 100 µA L3 130 nm I0 995 nA Fig. 8. Relative error between the calculated and the simulated distribution function of gm,1 . As it can be seen, the amplifier is designed in a way that M 1 operates in moderate inversion and the two transistors plotted because it is a 5-dimensional function. Therefore, only forming the current mirror operate in strong inversion. the error for gm,1 is shown, but the shown deviation applies The DC gain can be approximated by also for gds,1 and gds,2 . ⇣ ⌘ gm,1 Additionally, the shown calculation can be carried out for ID gm,1 every small signal circuit performance. ADC = ⇣ ⌘ ⇣sim ⌘ = . (16) gds,1 g + Ids,2 gds,1 + gds2 ID sim D sim VI. C ONCLUSION In this paper a design method is presented that allows de- The calculation of ADC follows the same scheme like signers to consider process as well as environmental variations that for IC and gm/ID . All conductances are time-dependent, and aging effect at early design stages. Moreover, the method therefore the expression for ADC already includes the impact shifts the simulation effort to a single transistor level by of aging and process/environmental variations. Moreover, it is generating a stochastic Look-Up Table. This leads to reduced possible to evaluate which is the most crucial parameter for simulation time and amount of data that must be stored. both effects at this very early design stage. Table IV shows With this data good predictions for small signal parameters a comparison of predicted fresh/aged ADC and those values of MOSFET and circuit performances can be derived. The simulated in C ADENCE. The initial amplification as well as the method is evaluated with the design of a common source impact due to aging is overestimated because the prediction amplifier showing only small errors in the prediction of the neglects the load resistance. initial distribution as well as for the degraded distribution. TABLE IV. C OMPARISON OF MEAN PREDICTED AND SIMULATED R EFERENCES FRESH / AGED ADC . [1] Maricau, Elie, and Georges Gielen. Analog IC Reliability in Nanometer Fresh Value Aged Value CMOS. Springer Science & Business Media, 2013. ADC,pre 93.1 dB ADC,pre 13.7 dB [2] Enz, Christian C., and Eric A. Vittoz. Charge-based MOS transistor ADC,sim 82.3 dB ADC,sim 19.12 dB modeling. John Wiley & Sons, 2006. [3] Hellwege, Nico, et al. Using operating point-dependent degradation and Figures 7 and 8 show the distribution for the simulated g m/I D method for aging-aware design. Integrated Reliability Workshop gm,1 as well as the relative error between the simulated and Final Report (IRW), 2013 IEEE International. IEEE, 2013. S. 113-116. calculated distribution. Around the mean value µgm,1 = 1 mS [4] Agarwal, et al. BSIM6.1.0 MOSFET Compact Model. University of the relative error is less than 3%. For lower and higher values Calirfornia, 2014. the error increases, but in order to fit this region another [5] Hillebrand, et al. Stochastic analysis of degradation and variations in distribution from the LUT has to be utilized. ADC cannot be CMOS Transistors, ZuE 2015. Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is published and copyrighted by its editors.