=Paper=
{{Paper
|id=Vol-1566/paper8
|storemode=property
|title=Ageing Impact on a High Speed Voltage Comparator with Hysteresis
|pdfUrl=https://ceur-ws.org/Vol-1566/Paper7.pdf
|volume=Vol-1566
|authors=Illani Mohd Nawi,Basel Halak,Mark Zwolinski
|dblpUrl=https://dblp.org/rec/conf/date/NawiHZ16
}}
==Ageing Impact on a High Speed Voltage Comparator with Hysteresis==
https://ceur-ws.org/Vol-1566/Paper7.pdf
25
Ageing Impact on a High Speed Voltage Comparator
with Hysteresis
Illani Mohd Nawi, Basel Halak and Mark Zwolinski
Electronics and Computer Science, University of Southampton
Southampton, SO17 1BJ, U.K
Email: {ibmn1g12,bh9,mz}@ecs.soton.ac.uk
Telephone: +44 (0) 8059 3081
Abstract—The impact of ageing on a high speed comparator sensitivity analysis significant results. Section V reported the
with hysteresis in 65-nm CMOS technology using SPICE NBTI analysis setup and the summary of impact of NBTI on
simulations is investigated. The comparator has been designed the SETs for a range of hysteresis voltage and 2 different input
to offer immunity to single event transients. The most sensitive frequencies. Finally, Section VI concludes our investigations.
transistor was subjected to single events at manufacture time and
after ageing, assuming a maximum parameter drift of 10% on
all PMOS transistors for 10 years. It was found that NBTI does
II. A IMS
not significantly affect the single event transient vulnerability of This work investigated the impact of NBTI on the SET
the comparator, at different hysteresis voltages. vulnerability of analogue circuits, in particular comparators.
Keywords: Single event transients, NBTI, comparator-with- As mentioned in our earlier work, [4], SETs in comparators
hysteresis, Schmitt trigger, synergism with no memory (feedback), are not problematic as they will
be propagated to digital circuitry and corrected at that stage.
However, an SET will likely cause a problem in a system
I. I NTRODUCTION with memory, particularly a comparator with hysteresis, such
CMOS scaling has been proven to improve a system’s as a Schmitt-Trigger. Schmitt triggers are generally used to
performance, however this has led to increased vulnerability increase the noise immunity of a particular device in an open-
to soft errors, particularly single event transients (SETs) as loop topology or used as bi-stable regulators and generators
reported by [1], [2], [3] for digital circuits and [4] for analogue in a closed-loop topology, and are widely used in aerospace
circuits. Although a single event transient caused temporary applications.
variations to devices, a single glitch could have a major effect In our previous work, [4], we noted that a high input
on safety critical applications, such as automotive, aerospace hysteresis voltage gives better noise immunity, but tends to
and aeronautical applications. ”trap” an SET. On the other hand, a low input hysteresis
In addition to the increased vulnerability to SETs, the voltage causes any SET to propagate, but reduces the input
aggressive scaling of CMOS devices has also increased noise immunity. There is, therefore a possible compromise
vulnerability to ageing, as reported by [5], [6], [7], [8], [9], between these two aims. Our aim in this work is to determine
[10]. [5] and [6] reported the impact of ageing on digital whether these two design aims, and any compromise between
circuits while [7], [8], [9], [10] focused on the impact of ageing them, are affected by NBTI-induced ageing.
on analogue circuits. To the best of our knowledge, there is no work which
studied the relationship between impact of NBTI and the SETs
While SETs and NBTI were individually investigated for
vulnerability in a comparator-with-hysteresis.
their impact on CMOS devices, limited work has been done
on the interaction between ageing and SETs [11]. Rossi et
al., [12], reported that NBTI would reduce the critical charges III. H IGH -S PEED C OMPARATOR I MPLEMENTATIONS
on the nodes of combinational and sequential circuits while Our comparator is based on a high speed comparator, [17],
Harada et al.,[13], reported that ageing has a significant impact as shown in Fig. 1. This comparator has been implemented
on the effect of SETs and Bagatin et al., [6], stated that previously in 120-nm technology and is able to work at up
NBTI degradation does not significantly affected the single to 20 MHz operating frequency [4]. We have improved our
event upset sensitivity of SRAM as long as the parametric previously implemented comparator, [4], to work at higher
drift caused by ageing does not exceed 10%. Additionally, frequencies, as we have found out that SETs introduced into
El Moukhtari et al., [14], has indicated a decrease in SET the previously designed comparator, which last less than 1
sensitivity under the influence of NBTI for chain of inverters clock cycle, will be propagated to the digital circuit and
and the same authors, [15], reported a fast increase of SRAM corrected there. This particularly applies to input frequencies
SET vulnerability under ageing. of less than 180 kHz. The same comparator has also been
used to study the interactions of various other factors on the
This paper is structured as follows. Section II outlines
vulnerability of SETs, at higher frequencies.
the aim of this work while Section III describes the im-
plementation of the comparator with hysteresis. Section IV In order to improve the operating frequency of the
summarizes the single event transient model used and the previously designed comparator, we have added a three-stage
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is
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26
pre-amplifier by Lin et al.,[18], as illustrated in Fig. 2. The in digital circuits are normally represented by either double
overall block diagram of the comparator-with-hysteresis is exponential waveforms or a square pulse. Although both
illustrated in Fig. 3. On top of this, we have also transferred models exhibit approximately the same total charge, it has been
our design to 65-nm technology as opposed to 120-nm used reported by [21], [22], [23], that the double exponential pulse
in our earlier work. The comparator now would be able to waveform has the most similarity to actual charge seen from
operate up to 1 GHz input frequency. heavy beam ion tests.
Fig. 4. Output error exhibited by transistor M21 for frequency of 10 MHz
and differential input amplitude of 400 mV
TABLE I. R ELEVANT EFFECTS OF ASET ANALYSIS
Fig. 1. 3-stage comparator diagram Vhyst 8 mV
Recovery time (ns) 506.9
Output error (cycles) 252.566
Pre-amplifiers Transistor M21
Recovery time (ns) 432.9
Output error (cycles) 222.8024
Positive feedback Transistor M16
Recovery time (ns) 391.1
Output error (cycles) 196.3353
Buffer Transistor M24
Most sensitive
Recovery time (ns) 400.5
Output error (cycles) 200.1499
Inverter Transistor M30
Recovery time (ns) 0
Output error (cycles) 0
Pre-amplifiers Transistor Various
Recovery time (ns) 213.9
Fig. 2. 3-stage preamplifier Output error (cycles) 107.057
Positive feedback Transistor M23
Recovery time (ns) 0
Output error (cycles) 0
Buffer Transistor M26
Least sensitive
Recovery time (ns) 388.4
Output error (cycles) 195.274
Inverter Transistor M29
Similar to our previous work, [4], we have injected
SETs into each transistor of the comparator with a double
exponential current pulse of 2 mA for 10 ns duration.
This approach is based on work by Zhao [19] and [24].
Narasimham, [25], proposed different points of injection on
PMOS and NMOS transistors, with the current source placed
between VDD and the source for PMOS and between the
drain and GND for NMOS transistors. Fig.4 illustrates the
transient response of the implementation of our high-speed
Fig. 3. Overall block diagram of comparator-with-hysteresis comparator-with-hysteresis, highlighting the output response
and the intermediate voltages with an input frequency of 10
IV. SET MODELING AND SENSITIVITY ANALYSIS MHz and an input amplitude of 400 mV. The output error in
Fig.4 reflects the SET suffered by the most sensitive transistor
Zhao et al., [19] suggested that the single event upset of the pre-amplifier, M21. The output error is reflected in the
(SEU) model, commonly used in analysis of soft errors in form of the number of clock cycles for which the comparator
digital circuits, can be used in the measurement of SETs in failed to sample a correct output value. The initial point of
comparators. As reported by [19], [20], single event transients output error occurs from the point of SET injection and the
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27
end point of the output error is when the output is returned VI. C ONCLUSIONS
to equilibrium, i.e sampled a correct value. The errors are
found by comparison with a radiation-free comparator. The The systematic approach of analysing the impact of NBTI
most sensitive transistor is obtained from SPICE sensitivity on the SETs on comparator-with-hysteresis has concluded that
analysis. NBTI has no significant impact on the SET sensitivity. From
the same analysis, we have observed the dependence of the
In our simulations studying the impact of variability on severity of SETs on input voltage frequency and hysteresis
SETs and other factors on SETs, we have identified the most voltage, which we are currently analysing. As for the NBTI
and least sensitivity transistors. This is to simplify our analysis effects on our comparator, the findings would only match
and to focus more on the interactions between the factors devices which are within the maximum parameter drift values.
rather than interactions within the circuit. Thus, similarly in Hence, as part of future work, similar analysis shall be
this work, we have performed the sensitivity analysis and Table extended to be modelled to have parameter drift exceeding
I summarizes the significant results for the comparator running 10%, in order to have a better understanding of the relationship
at a selected hysteresis voltage of 8 mV for an input frequency between NBTI and SETs. We aimed to come up with reliable
of 500 MHz. correlations between hysteresis voltage and SET immunity
under NBTI influence with extension of this initial work.
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Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is
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Fig. 5. Output error versus hysteresis voltage under aging impact, including aging-free for freq = 100 MHz
Fig. 6. Output error versus hysteresis voltage under aging impact, including aging-free for freq = 1 GHz
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This volume is
published and copyrighted by its editors.