-Many semiconductor circuit wearout monitoring techniques have been developed for different applications. This paper presents an overview of the prominent wearout monitoring techniques. We systematically categorize the semiconductor wearout monitoring techniques and qualitatively assess the different categories for the health monitoring application.
The rest of the paper is organized as follows. Section II briefly discusses the major wearout mechanisms. The most prominent monitoring techniques are categorized and assessed in Section III. The paper is concluded in Section IV.
The Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (NBTI), Hot Carrier
This work was partially funded by the European CATRENE RESIST subsidy project.
Injection (HCI), and Time-Dependent Dielectric Breakdown
(TDDB) are cited as major wearout mechanisms [
B. Causes of Wearout • • • • • •
Newer technology: Process scaling and high-K dielectric materials contribute to PBTI and TDDB.
mechanisms, like NBTI.
influences
the
wearout
Thermal cycling: The thermal cycling contributes to the
degradation of devices composed of multiple materials,
such as a semiconductor IC [
Supply voltage: Degradation depends on the supply voltage. In particular, the dynamic voltage scaling technique contributes to device degradation.
Amount of workload: The capacitive load driven by a
circuit has a correlation with the degradation [
Semiconductor wearout is a gradual process, which creates a chain of degradation events. It starts with the degradation of the threshold voltage as shown in Fig. 1. The threshold voltage degradation leads to a reduction of the drain current. As a result, signals take more time to travel through the datapath. This is indicated as the increasing circuit delay in Fig. 1.
A slight increase in the propagation delay may not immediately create a timing failure. It merely reduces the available timing margin of the datapath. At this point the circuit is still capable of functioning correctly albeit with a diminished timing margin. With the increase in stress conditions or continued aging, the timing margin diminishes to a point where a timing failure starts to occur. The degraded circuit may still function correctly at a slower clock speed and/or with relaxed operating conditions. However, a timing failure will occur at the normal operating conditions. As the aging process continues, the device eventually breaks down. At this point the circuit is not capable of functioning any longer. Different monitoring techniques to detect these indicators are discussed in the following section.
We first categorize the monitoring techniques based on where the function is implemented. We then categorize them further based on how the function is implemented. This categorization is shown in Fig. 2. The techniques highlighted in gray are discussed separately in the following sub-sections.
This technique applies different types of stress factors to
the target die for a period of time, removes the stress, and
performs an I–V measurement using external equipment. The
stress factors include temperature, voltage, thermal cycling,
and mechanical stress [
This technique allows the extraction and analysis of a large set of measurement data on powerful computing platforms. However, it relies on external measurement equipment, which is not suitable for run-time health monitoring application. To comply with the highest safety levels defined in the ISO26262, monitors need to be implemented independent from the circuit being monitored. This is to avoid a failure common to both the circuit being monitored and the monitor. Such common cause failures may result in an undetected error. Off chip monitors are well suited to avoid a common cause failure and can be an attractive way to abide by the ISO26262 recommendations. However, for run-time health monitoring purposes the off-chip solution needs to avoid relying on external equipment.
The on-chip monitoring technique can be realized in two different ways. The monitoring function can observe a circuit under stress that is not part of the datapath; or it can monitor the datapath itself. The former is called off-datapath monitoring and the latter is called on-datapath monitoring. The conceptual diagram of off-datapath monitoring is shown in Fig. 4. The analysis of the monitor observations may or may not take place on-chip, hence the dotted line around the analysis block.
The circuit under stress used in off-datapath monitoring can
be constructed by means of a dedicated circuit, or a modified
version of the datapath. This section discusses the off-datapath
monitoring by a dedicated circuit, e.g., a ring oscillator. A
stress voltage is applied to stress the ring oscillator and the
difference of its oscillator period before and after the stress is
used to measure the performance degradation due to NBTI [
TDDB causes the formation of a conductive path in the gate
dielectric layer. The circuit in [
There are monitors that can detect multiple wearout
mechanisms. The authors in [
This technique is suitable for process characterization and design optimization. However, there are two major problems related to the health monitoring application: 1. It is difficult to match the stress applied to the dedicated circuit to the stress experienced by the datapath. 2. Even if realistic stress is applied to the dedicated circuit, it is difficult to extrapolate the results to assess the actual degradation of the functional datapath.
Instead of a dedicated circuit, the circuit under stress can be
realized using a replica datapath. The replicated path, known as
the canary circuit, is designed such that it degrades faster than
the actual datapath. For example, the Vth degradation can be
induced by changing the body bias, oxide thickness variation,
and different W/L ratio. We can replicate a few timing-critical
paths and monitor their aging [
On-datapath monitoring addresses the limitations of offdatapath monitoring by observing the datapath itself. Based on when the datapath is observed, this technique is divided into off-line monitoring and on-line monitoring. The conceptual diagram of on-datapath offline monitoring is shown in Fig. 5.
Here, the datapath is monitored when it is not in the
functional mode. The datapath is excited by test patterns and
the test response is collected to analyze if any failure has
occurred. Structural tests for automotive In-Vehicle Network
(IVN) components have been presented in [
Here we observe the degradation of the datapath itself, and thereby avoid the inaccuracy caused by the extrapolation needed for the off-datapath monitoring technique. Since this technique provides a pass/fail result, it is limited to diagnosis purposes. It cannot make a prognosis of an imminent failure.
Online monitoring observes the datapath when it is in the functional mode and exercised by functional input signals. The conceptual diagram is shown in Fig. 6. The online monitoring technique observes the slack of the datapath considering its actual workload and on-chip effect. As the datapath degrades with aging, the slack of the datapath between registers gradually diminishes. Based on the resolution of the online slack monitoring, this technique can be sub-divided into two categories, namely, coarse-grained online monitoring and finegrained online monitoring.
For coarse grained monitoring, the slack is monitored to
yield a pass/fail indication. Different datapath slack monitoring
techniques have been reported in literature [
This technique does not require a dedicated circuit to stress, any stress signal, nor an extrapolation of observation. Since it only provides a pass/fail indication, the monitor can tell us if there is enough slack to meet the timing or not. In this way it provides an indication of a timing failure, but does not provide an indication of an imminent failure. As a result, it is suitable for diagnosis purposes, but not for prognosis purposes.
Fine grained datapath monitoring measures the slack with a
higher resolution to detect the gradual decrease of the available
slack and the diminishing timing margin. This technique can be
realized by the triple-latch monitoring technique, which is
developed to tune the clock speed [
The resolution of the slack monitoring can be improved by
using more than three samples. Drake et al. have presented two
versions of online slack monitoring [
Agarwal et al. describe a circuit failure prediction concept,
which enables close to best-case design instead of traditional
worst-case design [
The fine grained online monitoring technique observes the diminishing timing margin of aging critical paths, considering the effect of process variation, ambient conditions, and workload. However, monitoring the large number of datapaths of a typical design is not pragmatic. Therefore, monitors are designed to observe a few aging critical datapaths. However, aging depends on the field usage. Therefore, finding the aging critical datapaths during the design-time is challenging.
We categorize the available monitoring techniques and qualitatively assess their value for health monitoring. We have found that off-chip monitoring is “suitable by design” to eliminate common cause failures and can help fulfill the ISO26262 recommendations. However, their dependency on external measurement equipment needs to be avoided.
We find that the on-datapath techniques are particularly suitable for health monitoring. They need to be implemented independently from the circuit being monitored, for example by means of independent power supply, oscillator, etc. The following two techniques deserve further attention: 1. On-datapath offline monitoring becomes interesting when at speed tests are conducted. Since it operates at the functional speed, we can detect timing failures. Logic-BIST circuits can be used to realize at-speed monitoring. 2. On-datapath fine grained online monitoring is an interesting choice as it measures timing margins with higher resolution. However, finding the aging critical paths during the design-time remains a problem. Design-time analysis of critical path delays are performed using library cells whose delays are characterized for an output load and input slew with respect to a given PVT corner. To find out the path that would become critical during the lifetime of the chip we need an aging-aware library whose cells are characterized for load, slew and aging.