=Paper=
{{Paper
|id=Vol-1566/paper10
|storemode=property
|title=Static Aging Analysis Using 3-Dimensional Delay Library
|pdfUrl=https://ceur-ws.org/Vol-1566/Paper9.pdf
|volume=Vol-1566
|authors=Haider Abbas,Mark Zwolinski,Basel Halak
|dblpUrl=https://dblp.org/rec/conf/date/AbbasZH16
}}
==Static Aging Analysis Using 3-Dimensional Delay Library==
https://ceur-ws.org/Vol-1566/Paper9.pdf
34
Static Aging Analysis Using 3-Dimensional Delay
Library
Haider Muhi Abbas, Mark Zwolinski and Basel Halak
Electronics and Computer Science
University of Southampton
Southampton SO17 1BJ, UK
Email:{hma1g14,mz,bh9}@ecs.soton.ac.uk
Abstract—The growing concern about time-dependent perfor- This paper propose a method to inject the accurate calcu-
mance variations of CMOS devices due to aging-induced delay lation of the duty cycles derived from the application level to
degradation has increased with shrinking technology dimensions design new library targeting the aging prediction as a method
of the devices . One of the main causes of aging is Negative Bias called Static Aging Analysis(SAA). To achieve this we have
Temperature Instability (NBTI). Modeling NBTI-induced delay used a tool to derive the actual stress-recovery ratio of each
at gate level depends on the real stress activity of gate inputs
which are related to the workload applied from the higher level
logic gate from application then build three-dimensional look-
of abstraction (e.g. Application). Having estimated values about up tables for the NBTI-induced timing delays. To the best of
the degradation delays can make design stage to consider this our knowledge this is the first aging analysis method which is
issue as a design constrain and even to precisely allocate the based on predefined stress-probability library.
online aging sensors. this paper propose a method to include the
stress probability within technology library as three dimensional The organization of the remainder of the paper is as
look-up tables for Static Timing Analysis(STA) process of the follows. A concise review of the stress and recovery of NBTI,
design as an approach named Static Aging Analysis(SAA). the NBTI mitigation techniques and NBTI modeling are conferred
purpose of this approach is instead of estimating only the timing in Section II. Analysis of three-dimensional delay library is
delay at time zero, estimating NBTI-induced delays for predefined presented in Section III. Experimental setup and results are
lifetime of the product. given in section IV and finally Section V. concludes the paper.
Keywords—Negative Bias Temperature Instability (NBTI); Sig-
nal Probability; Static Timing Analysis. II. BACKGROUND A ND R ELATED W ORK
A. NBTI Stress-Recovery sources
I. I NTRODUCTION Basically, NBTI is generated due to a change in the phys-
ical characteristics of a transistor by generating interface traps
NBTI can lead to an increase in threshold voltage over at the channel and dielectric. The gates of PMOS transistors are
time. The first observations of a threshold voltage instability negatively biased with respect to the source (i.e. Vgs = Vdd ).
were made in the 1960s in MOS transistors, in which it was Generally, BTI consists of two different phases:
found that both bias and temperature affect the threshold volt-
age. From that time and until the year 2000, when introduction 1) Stress: Some interface traps are generated at the interface
of nitrogen atoms into the oxide was achieved, Bias Tem- of substrate/gate oxide layers due to applying electrical stress
perature Instability (BTI) remained unimportant phenomenon. (i.e. negative bias for PMOS) that leads to breaking of some
Since then, negative BTI has become a more important con- of the SiH or SiO bonds. Consequently, the threshold voltage
cern, both in academia and industry [1]. of the transistor increases over the time.
In general, there are two possible approaches of aging 2) Relaxation/Recovery: some of the generated interface
mitigation techniques either proactive or reactive. Proactive traps are removed from the interface. However, the relaxation
approach works as an estimator for aging behaviour and always phase cannot completely compensate for the effect of the stress
based on a model that describes how aging effects (NBTI, phase and therefore the overall effect of NBTI is a degradation
HCI and TDDB) are modeled by physicists in low level [2]– in the threshold voltage of the transistor. The amount of this
[4]. Usually this approach needs to take into account different degradation depends on the ratio between the stress period and
contributors of time-dependent variations (e.g. signal prob- the total period (duty cycle).
ability, switching activity, temperature and supply voltage).
Another approach is to monitor online the real behaviour of B. NBTI Mitigation Techniques
aging through delay sensors [5], [6]. The last approach is
more precise and short-cutting the complexity of modeling In this section, the literature of the mitigation techniques
the aging effects on the system level. However, the main used for aging is presented. A feasible solution to reliability
problem of online sensors is area overheads and to moderate problems including aging is to eliminate or even to reduce the
this drawback, limited numbers of nodes are needed to be design uncertainties that exist in current design technologies.
monitored. In order to define the locations and how many However, in practice, there is more than one contributor to
sensors to be inserted, offline analysis of aging is inevitable. these uncertainties including EDA tool limitations and complex
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This
volume is published and copyrighted by its editors.
35
environmental stress conditions [7]. Another solution is con- • For duty cycle (↵)=0.9, Vth increases by 210mV
servative design under the worst-case scenarios at the design (76%)
stage. However, circuits do not always run at the worst-case
condition and such an over-designed approach is extremely
costly in terms of power and area. At gate level, NBTI
manifests itself as time-dependent gate delay and finally leads
to timing violations. Adding some margins to the critical path
is not a solution because the critical path at time zero may not
still be the critical path after some years due to aging. Potential
Critical Paths (PCPs) or NBTI Critical Paths take into account
the effect of NBTI in static path analysis. In [8], critical gates
(gates within PCPs) are identified and optimization method-
ologies (i.e. gate resizing or reducing temperature) proposed
for these critical gates. However, NBTI has a dependence on
dynamic operation, such as supply voltage, spatial or temporal
temperature and signal probability and these parameters vary
dynamically from gate to gate. Another solution, proposed in
[9], uses signal probability to restructure the logic gates and
arrival times of the input signal to reorder the pins. However,
signal probabilities are assumed to be 50% for input signals
and for larger systems, signal probability is dynamic and based
on the application. Another technique to control NBTI is to
control the signal probability using the Input Vector Control Fig. 1. Vth degradation for different duty cycles.
(IVC) technique. However, both NBTI and leakage power have
a cross dependency on input patterns [4], [10].
III. 3-D IMENSIONAL D ELAY L IBRARY
C. Long-Term NBTI Model
The standard library that used to estimate the timing and
At device level, many models have been proposed as power at the synthesis stage based on pre-calculated look-
predictive models to simulate the real degradation in transistor up tables considering the input transition delay and output
performance. Until now, there is no universally accepted theory capacitance load as two-dimensional LUTs for each standard
or model, therefore all information is based on accepted cell in the library. To generate NBTI induced library for
experimental results. Reaction-diffusion (RD) is one of the the purpose of estimating the effect of NBTI for pre-defined
most prevalent NBTI models in the literature [8], [4], [11], lifetime of the product, three-dimensional LUT delay library
[3]. Many developments have been proposed to the model to could be built considering the Signal Probability SP(0) as
increase the accuracy of the model. The following formulas the third dimension along with input transition and output
describe the NBTI-induced degradation threshold voltage using load capacitance. Debatably, signal probability is not the only
long-term RD model: observable parameter from the application level to transis-
s !2n tor level, temperature is possibly observed as a function of
↵ switching activity of the transistor. However, the temperature
Vth = 2
Kv Tclk ( 1 ) (1)
1 2n is environment dependent and the spatial deviation of the
t
temperature in a small area is normally small. So, considering
the signal probability derived at the application level will not
⇣ qt ⌘3 p ⇣ 2E ⌘ estimate the degradation delay with 100% accuracy, but it will
ox ox
Kv = K 2 Cox (Vgs Vth ) Cexp (2) increase the accuracy of the estimation. Further optimization
✏ox E0
needs to be considered: for example, during the design phase,
p by restructuring the gates with high signal probabilities. Delay
2⇠1 tox +
⇠2 C(1 ↵)Tclk
t =1 p (3) sensors might also be inserted in a limited number of paths to
2tox + Ct consider other sources of ageing that are difficult to observe
↵ is the signal probability and it reflects the fraction of during the design phase (e.g. Temperature).
time spent in the stress state over a period of time, and
Tclk reflects the frequency of stress and recovery phases. IV. E XPERIMENTAL S ETUP A ND S IMULATION R ESULTS
The rest of the parameters are described in detail in [3]. We
simulate the 90nm technology node using MATLAB with the A. Signal Probabilities Extraction
following parameters: initial Vth = 0.276V, Vgs = 1.2V, T = We extract signal probabilities (duty cycles) of the nets
350K, tox = 2.15nm. Fig. 2. shows how duty cycles have a from different workloads using Mibench benchmark as work-
big impact on Vth degradation. load on OpenRisc 1200 processor (see TABLE I and Fig.
3.).To obtain the duty cycles (signal probabilities SP(0)) of
• For duty cycle (↵)=0.1, Vth increases by 130mV
the nets for a specific application, we started from the VCD
(increases 47% from the initial Vth )
file to obtain SP(0). The VCD file implicitly contains both
• For duty cycle (↵)=0.5, Vth increases by 180mV switching activity that is used to estimate the dynamic power
(65%) at the design phase and the signal probability that we use
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This
volume is published and copyrighted by its editors.
36
to estimate the NBTI effect on performance degradation. So, delays that used as an input parameter to calculate the prop-
we built a compiler using open source software (JFLEX and agation delay for the next cell. To induce signal probabilities
CUP) available in [12] to generate a file contains the SP(0) SP(0) into the library, we used HSpice simulation to generate
for all the nets of the processor. Getting VCD file for the the timing delays. the figure Fig. 4. shows the output rising
gate level needs to simulate the post-synthesized processor. We delays when the SP(0) barely stressed and the figure Fig. 5.
synthesis OpenRisc using 90nm Technology from Synopses shows the output rising delays when the SP(0) almost totally
using limited number of netlists that have only one level of stressed. the results show that up to 81% difference between
transistors to avoid getting hidden signal probabilities inside the the cases mentioned above. Choosing how many steps for
the multilevel cells. The results show that there is likely stress SP(0) would define the complexity of the delay calculation
probability within the nets with different workloads and the inside the Static Aging Analyzer. So, some specific steps need
signal probability highly related to the architecture rather than to be calculated and any other intermediate values could be
the workload as shown in the Fig. 3.). either taken the worst case or interpolated from two points.
TABLE I. S IGNAL P ROBABILITIES P ERCENTAGES FOR M IBENCH
W ORKLOADS
Automotive Telecomm Network secuirty
SP(0) Range qsort susan adpcm crc fft dijkstra sha
0-0.09 26% 20% 24% 20% 24% 20% 20%
0.1- 3% 3% 0% 3% 0% 3% 4%
0.2- 4% 3% 2% 2% 2% 3% 3%
0.3- 2% 2% 2% 2% 2% 1% 1%
0.4- 3% 3% 2% 2% 2% 3% 3%
0.5- 7% 5% 4% 5% 4% 4% 5%
0.6- 4% 2% 3% 3% 3% 2% 2%
0.7- 9% 6% 4% 6% 4% 3% 5%
0.8- 4% 6% 1% 7% 1% 8% 6%
0.9-1 39% 51% 58% 51% 58% 53% 51%
Fig. 3. Output Rising Delays when SP(0)=0.1.
Fig. 4. Output Rising Delays when SP(0)=0.9.
V. C ONCLUSION AND F UTURE W ORK
Fig. 2. Horizontal axises: Compressed information about the net names of
This work has proposed an approach to include the signal
OpenRisc Processor, vertical axises: Percentages of Signal Probabilities SP(0) probabilities driven from the workload to the gate-level timing
for MiBench Workload. library. This work could make estimating NBTI-induced delay
more feasible during the design and could help to abate the
number of aging sensor and location. However, this approach
B. Three-Dimensional LUT Generation
required a logic synthesizer to read these three-dimensional
Basically, the library file contains four look-up tables, two LUT and may make optimization during cell mapping to re-
for rising and falling propagation delays, and two for transition duce highly stressed signal in the critical path. Future work will
Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This
volume is published and copyrighted by its editors.
37
consider the use this table by building this logic synthesizer to
identify the most vulnerable part for aging in the processor.
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Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Copyright © 2016 for the individual papers by the papers' authors. Copying permitted for private and academic purposes. This
volume is published and copyrighted by its editors.