This paper presents a combined fault detection and discrimination strategy for CMOS logic incorporating active resource mitigation and monitoring. The approach is demonstrated for a NOR gate using a dual redundant gate design with selective mitigation and analogue or digital detection. The potential bene ts of the approach are discussed with respect to resource awareness and management within ne-grained logic.
Fault detection and mitigation within CMOS logic structures is a long-standing
challenge that is seeing new a emphasis for nanoscale and printable electronics.
The possibility for intrinsic resource awareness and management without
obfuscating management at higher design levels is an attractive proposition but
requires new gate and transistor level strategies. This paper presents ongoing
work into a combined ne-grained redundancy and active mitigation approach
with minimal resource overhead that enables selective fault detection, masking
and discrimination close to the point of fault manifestation.
On-line fault strategies have been discussed at length for future nanoscale
electronics where massive redundancy concepts become feasible [
A Combined Fault Detection and Discrimination Strategy c type becomes abstracted by the internal process of converting critical faults to sub-critical faults.
Fine-grained fault tolerant strategies are beginning to feature in future
nanoscale CMOS logic design with the principal aim of combating manufacturing
defects. This includes psueo-CMOS redundancy, a simple example of which is
illustrated in Fig. 1c. Another approach is reported in [
Field-programmable gate arrays (FPGA) provide exible platforms
featuring con gurable cellular architectures that support full or partial con guration.
Since their total resource utilisation rarely approaches 100%, there are
opportunities to provision redundant resources for fault mitigation. Even so, it is not yet
clear how spare resources may be reallocated to support online fault detection
and discrimination without resorting to external supervisory hardware/software
as typi ed in [
The proposed strategy relies upon an alternative method referred to here as
Stuck-At Fault Resilient (SAFR) design, wherein xed dual redundancy is
combined with a fault triggering mechanism [
Discrimination and Mitigation
Selective fault masking allows for the detection of stuck-on faults considered to
be critical due to potential high current ow between VDD and GND.
Examination of the gate output response under fault condition, summarised in Table 1,
shows that at there is at least one input combination that generates current ow
between VDD and VSS for every single stuck-on fault. This may be exploited
to achieve discrimination of fault type by monitoring current imbalance in the
CMOS network or else periodic exercising of the gate inputs via digital test. The
P- and N-networks are combined with the switching network for a NOR gate
implementation are shown in Fig. 3, which includes weak active pull-up/down
loads typically used for defect repair [
Resource considerations will be important for emerging printable and nanoscale electronics due to their di ering densities and scope for building redundancy structures based upon multi-gate and/or sub-gate nano-structures. Resource management extending to the ne-grained levels should be explored for both defect tolerance and hard-fault mitigation. Combining the above approach with weak active pull-up/down loads creates an e cient active mitigation mechanism that, when further combined with dual redundancy within the P- and
A Combined Fault Detection and Discrimination Strategy
A B
T1 T3
VDD T2
T4 (a)
GND
A+B T5
T6
T7
T8 k r o w t e N P k r o w t e N N
S1 S2 (b)
S3 VDD S4
VDD N-networks, creates further resource awareness opportunities in the presence of faults. Once a fault has been detected, partial isolation proceeds by switching to pseudo-NMOS or PMOS mode wherein the nature of the fault may be further characterised. For example, assuming a stuck-at high fault occurring within the P-network (Transistors T1-T4 in Fig. 3a), the location of the fault is not known a-priori. The circuit may rst be switched to pseudo-NMOS mode (setting switches S1 and S3 in Fig. 3b) and, due to the complimentary nature of the design, a second analogue/digital test will would reveal the same fault behaviour summarised in Table 1. However, depending on the value of the weak pull-down resistance of transistor T9, the digital test may pass without error and the adapted circuit may continue to be used in a degraded state. Alternatively, the circuit may be switched into pseudo-PMOS mode (switches S2 and S4) whereupon the error no longer persists. Hence the state of the P- and N-networks may be individually ascertained. The reverse situation of a fault occurring within the N-network would proceed in identical fashion as described above. At all times stuck-at low fault events are intrinsically masked. 5
An further extension of resource awareness concerns continual resource monitoring in the presence of intermittent faults. For the above case of the pseudoPMOS con guration being activated in response to a stuck-high fault within the P-network, a further option would be to periodically switch to the pseudoNMOS con guration and check the P-network response to determine whether the fault persists. This serves two functions: rst, intermittent faults may be handled in a graceful manner and with speci c knowledge of their locality. Second, disappearance of the fault allows for restoration of the full CMOS network and non-degraded performance. 4
Fault detection and discrimination remains a fundamental challenge in resource management for integrated fault mitigation. The proposed dual redundancy SAFR method achieves a combination of fault discrimination between stuckhigh/stuck-low fault events and selective masking, thus reserving active mitigation for stuck-high faults. Fine-grained resource mitigation proceeds by combining redundancy with weak pull-up/down networks. Ongoing work is investigating further logic gate con gurations and functional logic built from such gates.
This work was supported by the UK EPSRC Centre for Innovative Manufacturing in Through-life Engineering Services (EP/I033246/1).