As new technologies use a reduced transistor size to improve performance, circuits are becoming remarkably sensitive to soft errors that become a serious threat for critical applications reliability. Most of the existing reliability enhancing techniques lead to costly hardware. The masking phenomenon is fundamental to accurately estimating soft error rates (SER). The rst contribution of this paper is a new crosslayer model for input-dependent Single Event Transient (SET) masking mechanisms combining Transistor Level Masking (TLM) and System Level Masking (SLM). We, secondly, use this model to build an autotuning fault tolerant circuit dedicated to obstacle detection systems in railway transportation. Based on our input-dependent masking model, the proposed architecture evaluates the e ective circuit's vulnerability at runtime and accordingly adapts the reliability boosting strategy, leading to a reliable circuit with optimized overheads. When compared to the Triple Modular Redundancy, our technique reduces the number of FPGA LUTs (resp. DSP slices) by up to 45% (resp. 33%).
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Ihsen Alouani, Smail Niar, Yassin El-Hillali, and Atika Rivenq
In this paper, we present ARDAS for Auto-tuning Redundancy in DSP-based Architectures for Soft errors resiliency, an architecture that uses auto-tuning redundancy of DSP blocks to protect the vulnerable circuit parts instead of protecting the whole circuit. The vulnerability analysis is performed through design-time simulations that implement the proposed masking models (TLM and SLM). 2
TLM occurrence is led by the a ected transistor locality within the struck gate as well as the input combination during the transient event. In fact, the particle strike temporarily corrupts combinational elements by a ecting the state of the hit transistor. However, the event can be simply unnoticed at the output if the transistor behavior corruption doesn't a ect the overall state of pullup/pull-down network. Let be Di a binary variable set to 1 if the error due to a particle strike hitting a transistor Qi is masked by a TLM mechanism. Pi is the probability that Qi is the hit transistor within the struck gate by the particle. Hence, the probability that the error resulting from a radiation strike in gate j is masked for a given input combination in gate j is then expressed by: PT LM (j) = PiN=j1(Pi Di). For simplicity, we assume the equiprobability of gates' transistors to be hit by a particle. Let Nm be the number of cases the error is masked for a given input combination. Hence, PT LM (j) = NNmj .
The probability of soft error masking in the output bit Si of a combinatorial circuit for given input signals is:
P miasking = n X Wj (PT LM (j) + (1 j=1
PT LM (j)) Dij ) (1)
Where n is the number of gates in the circuit, PT LM (j) is the probability of TLM at gate j and Wj is the weight assigned to gate j, expressed as the number of the gate's transistors divided by the total number of transistors in the circuit. Finally, Dij is a binary variable set to 1 if the error at gate j does not propagate to output Si and to 0 otherwise. 3
In a threshold-based system, the comparison of the intermediate result with a beforehand xed threshold gives the overall system decision. A transient error in the intermediate result may keep the overall system decision unchanged depending on the detection threshold value.
We consider a widely used signal processing element in detection/recognition
applications, namely a correlator. We built a simulation tool that tracks the
propagation of event-induced errors happening within the correlator nodes and
evaluated their impact on obstacle detection accuracy. The correlator is implemented
using DSP48E1 slices [
We de ne Vj , the vulnerability of a DSPj by:
Vj =
PNj i=1 ij (1
Nj
Pij )
(2)
Where: Nj is the number of output bits of DSPj , Pij is the probability of TLM
relative to bit i of DSPj and ij is a variable set to 0 if a fault at node (i; j) is
masked by SLM, i.e. ij 0 and is equal to 1 otherwise. We localize vulnerable
DSPs as those with Vj > V0 and de ne j as follows: j = 0 if Vj > V0
and j = 1 if Vj V0. As [Vj ] vector depends on the applied input signals,
the redundancy distribution corresponding to the vulnerability map has to be
dynamically tunable and self adaptive. The main idea is to judiciously use the
redundant DSP slices to carry out an auto-tuning partial TMR instead of a full
TMR. The system adapts the redundancy to the actual vulnerability map of the
circuit using the circuit's [ j ]; 8j 2 [1; Ndsp].
The recon guration process used to change the redundancy mapping at
runtime is taken from our previous work [
In addition to the reliability, we investigate the impact of ARDAS on power consumption, resource utilization and the maximum clock frequency of each circuit for two vulnerability threshold values: 0:55 and 0:7. The circuit is synthesized for a Xilinx Virtex 7 board. The power consumption is estimated using the Xilinx XPower Analyser tool. Table 1 shows that our architecture reduces the reliability cost in terms of resource utilization, power and performance. In fact, ARDAS decreases the number of used LUTs by 10% for V0 = 0:55 and by 32% for V0 = 0:7 compared to TMR. On the other hand, while using TMR slows
Fig. 2. Normalized SER (left axis), used DSP resources vs V0 (right axis) 5 down the circuit frequency by 42%, ARDAS performance penalty is less than 18% compared to the unprotected circuit. 6
In this paper, a self adaptive reliability approach is proposed to cope with the increasing error rates in new technologies with the lowest possible overheads. ARDAS relies on an auto-tuning redundancy architecture to protect the vulnerable parts of the system rather than the whole circuit. Due to its quick recon gurability, ARDAS o ers high reliability with reduced overheads. Moreover, it allows designers to choose the desired reliability level depending on the application requirements and its criticality.