The upgrade of the Large Hadron Collider, scheduled for 2019-2020, will increase the instantaneous luminosity by more than three, hence the ATLAS trigger rates. To cope with this increase, the trigger signals from the ATLAS Liquid Argon Calorimeter will be rearranged in 34000 so-called super cells to get a 5 to 10 times finer granularity. This will improve the background rejection performance through more precise energy measurements and the use of shower shape information to discriminate electrons, photons and hadronically decaying tau leptons from jets. The new system will process the super cell signal at 40 MHz and with 12 bit precision. The data will be transmitted at 5.12 Gb/s to the back-end system using a custom serializer and optical transmitter. To verify full functionality, a demonstrator set-up has been installed on the ATLAS detector and operated during the LHC Run 2. This document gives a status on hardware developments towards the final design readout system, including the performance of the newly developed ASICs. Their radiation tolerance, the performance of the prototype boards, results of the high-speed link test with the prototypes and the performance of the demonstrator with collision data are also reported.
The ATLAS experiment [
The Liquid Argon Calorimeter (LAr) is a sampling calorimeter with liquid argon as the active medium. Its scheme is shown in Figure 1. In the electromagnetic barrel and end-caps (EMB and EMEC) it consists of accordion shaped lead absorbers and copper/kapton electrodes. The hadronic end-caps (HEC) use copper absorbers and copper/kapton electrodes and the forward calorimeter (FCAL) involves copper absorbers in the electromagnetic section and tungsten absorbers in the hadronic section. The LAr Calorimeter plays a crucial role in the electron and photon reconstruction as well as jet identification and missing transverse energy measurement. It consists of 182000 readout channels with 1600 front-end boards (FEBs) and 200 readout driver boards (RODs) at back-end.
The LAr Calorimeter is currently read out at two stages, which are the regular and the trigger readout. In the regular readout the calorimeter cell signals are amplified, shaped and sampled in the FEBs for each bunch-crossing at 40 MHz and digitised and transmitted upon a L1 trigger decision at 100 kHz. The trigger readout uses a reduced granularity by summing signals from calorimeter cells on the Layer Sum Boards (LSBs) and on Tower Builder Boards (TBB) to form analog trigger tower signals, which are sent off-detector to the L1 Calorimeter Trigger System (L1Calo) for each bunchcrossing at 40 MHz.
The plan for LHC and high-luminosity LHC (HL-LHC) is presented in Figure 2. The currently on-going Run 2 will be followed by the long shut-down 2 (LS2) during 2019/2020, in which the Phase-1 upgrade system will be installed. The Phase-2 upgrade is foreseen for 2024–2026 during LS3.
The current L1 trigger system uses trigger towers with a 0.1 × 0.1 pseudo-rapidity × polar
angle size in the EMB as input from the LAr Calorimeter. The Phase-1 upgrade of the LAr
Calorimeter readout electronics [
The connectivity, cross-talk and noise performance has been verified for the standard baseplanes for EMB and EMEC with prototypes and the production has started. The development of the special base-planes for EMEC, HEC and FCAL is progressing. The procurement of common parts such as ground springs and alignment pins is ongoing. The FEBs will remain unchanged until Phase2, but the LSBs will be replaced to comply with super cell signal summing. Their production is ongoing.
There are a total of 124 LTDBs reading 34 thousand super cells to be installed. Each LTDB reads up to 320 super cells. It digitizes analog signals with 12 bits at 40 MHz using custom analogto-digital converters (ADCs). The digital signals are transmitted using 40 optical links at 5.12 Gb/s with custom application-specific integrated circuits (ASICs). It has 5 GigaBit Transceiver (GBT) serializer-de-serializer links for trigger, timing and control (TTC) signals. Its power distribution board (PDB) has to comply with the total power consumption of around 125 W.
The whole system is on the detector and thus, all components need to be radiation-tolerant. It has full compatibility with the Phase-2 upgrade. The final design has been fixed and prototypes are being produced.
Each LTDB requires 80 custom ADCs that continuously process the sampling and digitization of four super cell signals at 40 MHz. The power dissipation is less than 50 mW per channel and the latency must be less than 200 ns. The dynamic range is 11.7 bits per sample.
The Nevis13 ADC fulfils all requirements. Its layout is based on a 130 nm IBM CMOS 8RF of 3.6 mm × 3.6 mm with 72 quad-flat no-leads (QFN) pins. It uses four multiplying digital-toanalog converters (MDACs) for the most significant bits and one successive approximation ADC (SAR) for the lower 8 bits. It is tested for radiation up to 10 Mrad which corresponds to 100 times more than currently expected at HL-LHC.
Two kinds ASICs for optical links on the LTDB are developed. The serializer (LOCx2) is based on a 250 nm silicon-on-sapphire technology with a die of 6.0 mm × 3.7 mm and 100 QFN pins. Its output is at 5.12 Gb/s at a latency of less than 75 ns. It has about 1 W of power consumption. The laser driver (LOCld) uses the same technology as the LOCx2 on a die of 2.1 mm × 1.1 mm and 40 QFN pins. It is a dual-channel vertical-cavity surface-emitting laser (VCSEL) driver.
Both ASICs have been tested on radiation-tolerance. Only few change in the output eye diagrams has been observed after about 200 kHz. The wafers are produced and tests on the LTDB prototypes are ongoing.
The LDPS receives the digital 12-bit data from the front-end system. It calculates the transverse energy of each super cell and various sums of super cells at fixed latency and transmits the results at 40 MHz to the L1Calo feature extractors. Additionally it buffers the calculated results for a readout upon L1 trigger decision for debugging and monitoring. Because the back-end LDPS is offdetector, there is no need to be radiation-tolerant as the front-end system.
Its main component are about 30 LAr Digital Processing Blades (LDPBs) which read the
outputs of 124 LTDBs. Each LDPB consists of one LAr carrier board (LArC) with four advanced
mezzanine cards (AMCs) and a rear transition module (RTM). It is a custom advanced
telecommunications computing architecture (ATCA) board and uses a Xilinx Virtex7 FPGA. It carries
four AMCs and drives the communication to the FELIX system [
The LATOME receives super cell data from the LTDBs at 5.12 Gb/s on up to 48 optical
links. It is responsible for the computation of transverse energies of super cells and sums of super
cells using optimal filtering algorithm (OF) [
The LAr demonstrator is a pre-prototype of the calorimeter readout of the L1 trigger processors installed in 2014 during LS1 at the ATLAS experiment. It covers 3.1 % of EMB and is located in pseudo-rapidity 0 < η < 1.4 and azimuthal angle 1.77 < φ < 2.16. Before its installation no disturbance to the current system has been verified. It validates the energy reconstruction and bunchcrossing identification development. The system is successfully calibrated and data from protonproton (and heavy-ion) collisions is taken during the on-going Run 2. Two LTDB prototypes provide the analog summing of calorimeter cell signals to super cells at the rate of 40 MHz. The AMC prototypes are the so-called ABBA (ATCA board for a baseline of liquid argon acquisition) boards. It is planned to replace the two LTDBs and the LDPS by final prototypes in early 2018.
The two LTDBs handle each up to 320 super cell signals (284 super cells in EMB). The super cell signals are digitized with a commercial, not radiation-tolerant 12 bit ADC (TI ADS5272). On one 4.8 Gb/s optical link eight super cell signals are multiplexed. Two prototypes with different technology have been developed by several institutes. The first one uses an analog mezzanine and a digital main board and the second one uses a digital mezzanine together with an analog main board. Both versions are successfully operated during Run 2.
The ABBA board receives the digital signals of up to 320 super cells from one LTDB on up to 48 optical links at 4.8 Gb/s. It stores the ADC super cell data in circular buffers and sends it using the IP-based protocol IPbus over user datagram protocol (UDP) on a 10 Gb Ethernet upon a L1 trigger accept in the so-called “monitoring mode”. It contains three Intel (former Altera) Stratix4 FPGAs, which is shown in Figure 6.
In calibration electronic pulses are sent by calibration board and measured by the demonstrator readout. Figure 7 shows ADC pulse measurements and noise level for different super cells. Good linearity has been observed up to DAC 8000, beyond that analog saturation is expected. The noise level is well below 1 ADC count for all super cells and consistent with test bench measurements.
The ATLAS LAr calorimeter electronics will be upgraded during the LS2 (2019-2020). The trigger path will be digitized at the front-end level with increased granularity. New LTDB (front-end) and LDPS (back-end) systems have been developed. The digitization and readout of this system will be done at 40 MHz. Specific radiation tolerant ADCs and optical links have been designed and tested for the LTDBs. The production will be started in 2018.
A demonstrator system has been installed and successfully run since 2015 for data-taking from proton-proton and heavy-ion collisions. This gives valuable data to study the filtering algorithm development for super cell energy measurement. It is planned to replace the LTDB and LDPS with final prototypes in early 2018 to test the full pre-production readout chain with proton-proton collision data in 2018. The Phase-1 upgrade is a stepping stone towards the full readout upgrade in Phase-2.