Coarse-Grained Reconfigurable (CGR) architectures combine high performance with flexibility, allowing the execution of a large set of applications over the same substrate. However, they are also required to be energy efficient. This work focuses on a methodology to identify which parts of a CGR architecture may benefit from the application of power saving techniques, guiding the designers towards an optimal implementation of clock gated and power gated designs.
Nowadays small portable devices are required to efficiently execute multiple fancy functions. Reconfigurable systems [1] are a suitable solution for these colliding requirements. In particular, Coarse-Grained Reconfigurable (CGR) systems offer higher performance with a certain degree of flexibility. In CGR systems all the resources belonging to the possible configurations are instantiated in the substrate, and they are multiplexed in time. Thus CGR offer fast reconfiguration, paying the cost of the power consumed by the resources present in the substrate but not involved in active configuration.
Power consumption in digital devices is computed as in Equation 1, where: 1) P lkg is the static power dissipation caused by leakage currents, consumed even while no circuit activity is present; 2) P int is the dynamic power consumption mainly due to the cell switching activity; (3) P net is again a dynamic term, related to the interconnection. With technologies below 90 nm, designers are required to minimize both static (P lkg ) and dynamic (P int + P net ) terms. of several resources (i.e. sleep transistors to switch on/off the power supply, isolation cells to avoid the transmission of spurious signals and state retention logic to maintain the internal state of the gated region) and the rules to manage them are quite complicated, thus commercial tools do not provide it automatically.
In a CGR architecture, considering the minimum set of disjointed Logic Regions (LRs), composed of processing elements that are always active/inactive together, it is possible to apply to all of them CG or PG techniques. However, if on one hand CG requires only one AND gate for each region to switch off the clock tree, PG has a much higher cost due to the additional logic, and the power overhead may easily overcome the power saved by switching off the unused resources. The research presented in this paper studied an automatic system-level analysis and implementation flow to estimate in advance the cost of CG and PG application in a CGR system, leading to the identification of those LRs that can benefit from the application of these power saving techniques.
The proposed model (see Equations 2 and 3) estimate P lkg and P int of Equation 1, when PG and CG are applied at LRs level. They are composed of two terms: 1) P lkg/intON (LR i ) -consumption within the considered LRs; 2) Ext Over lkg/int (LR i ) -consumption due to the logic inserted outside the LR.
In particular, the Equations present the following contributions:
-Combinatorial Logic [P lkg/int (cmb) * T i ON and P lkg/int (cmb)]: sum of the contributions of the combinational cells, weighted for the activation time T i ON . CG switches off only the clock tree; therefore, combinational logic is always active when CG is applied. -Sequential Logic [P lkg/int (reg) * (#reg−#rtn)/#reg * T i ON and P lkg/int (reg) * T i ON ]: this term consider only those registers (#reg) inside the LR that are not replaced by the retention cells. CG does not have effect on the static power, thus when it is applied only the internal contribution is multiplied by T i ON (P lkg (reg) and P int (reg) * T i ON ). -Retention Cells [P lkg/int (RC) * #rtn * T i ON )]: This term consider the retention cells inserted to preserve the status of some registers (#rtn), when PG is applied. P lkg/int (RC) is the consumption of a single retention cell.
#iso]: In the PG case, isolation cells are inserted and their dissipation is proportional to their overall number.
Clock gating cells are used in both PG and CG cases. In the PG case they are required for the proper operation of the retention cells.
inserted to properly drive the enable signals to the power saving logic.
This estimation model has been embedded in the automatic design flow for CGR systems offered by the Multi-Dataflow Composer (MDC) tool [2]. MDC handles the automatic composition and deployment of CGR systems, starting from the high-level specification of the kernels to be executed, represented as networks [3]. MDC offers also other functionalities: 1) a structural profiler that performs the design space exploration of the implementable multi-functional systems to determine the optimal CGR substrate [4]; 2) a power manager that partitions the multi-functional network, identifying the minimum set of disjointed LRs and applies to all of them either CG [5] or PG [6] (generating an ad-hoc common power format (CPF) file to specify the power intent early in the design [7]); a rapid prototyper to embed the CGR system into a Xilinx compliant IP [8,9]. The MDC power manager has been extended to analyze the design, exploiting the estimation flow, to identify which regions may mostly benefit of PG and CG application [10,11]. Fig. 1 shows the complete analysis and implementation flow. MDC derives the HDL code of the baseline CGR system and provides the scripts to perform the synthesis and all the simulations for the system back annotation. Commercial tools are used to determine the baseline system power reports, which are fed back to MDC. MDC identifies the LRs and estimates the number of isolation cells (#iso) at dataflow level by analyzing the connections between the different LRs. These data, together with the information gathered by the reports of a single synthesis run of the baseline CGR system netlist, are used to estimate power consumption of the identified LRs (consumption of the additional power saving logic -isolation cells and retention cells is estimated by characterizing the adopted technology libraries). The power estimation flow analyzes the LRs according to Algorithm 1:
area evaluation: PG overhead may affect the power consumption of the smaller LRs. Thus, too small LRs are evaluated only for CG application. The threshold value is set by the user. -PG evaluation: the power variations due to PG and CG application are estimated. If PG results more convenient than CG, the LR is candidated for the implementation of PG application. Otherwise, CG is evaluated. -CG evaluation: the power variation due to CG application is estimated. If it is not able to save any power, LR is discarded and its logic will be included in the always on domain.
To assess the proposed methodology, two different applications are considered, an FFT application and a computing core accelerating a zoom application. The Fast Fourier Transform (FFT) [12] is an optimised algorithm for the Discrete Fourier Transform (DFT) calculation; a DFT of size 2 (radix-2) takes the name of butterfly. The adopted use case involves a CGR radix-2 FFT of size 8, where 4 different configurations are available, FFT that uses: 1) 12 butterflies; 2) 4 butterflies; 3) 2 butterflies; 4) 1 butterfly. In this design MDC identified 8 LRs. The Zoom coprocessor is composed of seven computational kernels: 1) absolute value calculation; 2) Bilevel/grayscale block checking; 3) Linear combination calculation; 4) Cubic filter convolution; 5) Median calculation; 6) Maximum/minimum finding; 7) Edge block checking. These kernels have been modelled as networks and implemented over a CGR hardware accelerator. In this CGR co-processor MDC identified 13 LRs. To validate cross-application and cross-technology effectiveness of the proposed estimation model, this section presents assessment on three implementations: FFT targeting a 90 nm CMOS technology; Zoom targeting a 90 nm CMOS technology; Zoom targeting a 45 nm CMOS technology.
These designs have been synthesized using Cadence RTL Compiler, then generated post-synthesis simulation reports have been fed back to MDC tool to estimate the power consumption of gated LRs, by applying Equations 2 and 3. In order to calculate the accuracy of the proposed estimation models, one power gated and one clock gated design for each identified LR have been implemented. Tab. 1 reports the real (extracted from the post-synthesis reports) and estimated percentage power variation for each LR, respectively when CG and PG strategies are applied. Comparing real power variations with estimated ones we see that the worst estimation is related to LR4 of FFT, whose percentage power variation is so low (-0.67%) that it is impossible to estimate it accurately. For this reason, the algorithm that evaluates the LRs keeps in consideration also their area.
Tab. 1 also depicts the percentage area of each LR with respect to design area. As expected, biggest regions (LR1 in FFT and LR2 in Zoom) are the ones with the highest power saving, regardless of the considered strategy (PG or CG). Also the composition of the considered LR has an impact on the effectiveness of the applied power saving technique. LR1 of FFT is 99% combinational, thus CG can save really little amount of power in this region. However, simply considering the LR size may not be sufficient to identify the best candidate for power saving; indeed it is possible to notice that LR3 of FFT is 15.8% of total area, but switching it off only saves about 6% or total power.
The presented methodology speeds-up the evaluation of power saving application estimating in advance the effectiveness of PG or CG if applied to the LRs of a CGR system. For a CGR system composed of N input networks, only one of the baseline design without any power management, and N (one for each kernel) simulations to retrieve the real switching activity of the system, are required. Otherwise, it would be necessary to implement a design for each identified LR for both CG and PG applications, plus the baseline one (to evaluate the cost and benefit of the chosen power saving technique).
As a follow up of this research it is necessary to improve the model, considering in the power estimation also the contribution of the interconnection which currently is not addressed. Furthermore, power switches overhead is not considered yet; these sleep transistors are inserted only during place and route flow, and a way to estimate in advance how many switches are going to be inserted for each LR has not been explored yet. The number of switches has effect on the rush currents during power-up transitions, and on the power-down/up timing, thus also these issues are going to be addressed in a future work.
To the best of our knowledge, literature does not treat the problem of modeling PG and CG costs in CGR designs. Shafique at al. [13] focuses on low-power techniques and power modeling for FPGAs. In [14], only CG is taken into account: different power states are defined and their consumption is characterized by low-level power analysis results. The work in [15] focuses on estimating the leakage reduction for PG and reverse body bias.
Other approaches perform an estimation that considers different components. For instance, Stokke at al. [16] propose a power modeling method for the Tegra K1 CPU, that taking into account measured rail voltages and fine-grained hardware activity predictors, expose components such as rail and core leakage cur-rents. The FALPEM framework [17] provides power estimations at pre-register transfer level (RTL) stage, specifically targeting the power consumed by clock network and interconnection, but PG and CG costs are not defined. Finally, Li et al. [18] propose an architecture-level integrated power, area, and timing modeling framework for multi-core systems, that evaluates system building blocks (i.e., CPU, buses, etc.) for different technology nodes, providing also PG support.