Today, the demand of adaptive systems is constantly growing, especially in hard-constrained contexts such as Cyber-Physical Systems. However, the e cient management of such platforms requires dealing with several issues such as the real-time execution, energy saving and dynamic context changes. Such strict requirements imply a high exibility of the application and of the architecture on which it is executed. Runtime managers o er the possibility to dynamically schedule and map an application on the available software processing units. However, hardware acceleration may also be necessary for computationally-intensive workloads that depend on the running functionality, additionally complicating runtime management. Coarse-Grained Recon gurable (CGR) accelerators have the ability to switch among di erent domain-speci c functionalities with a small overhead. To support energy and time adaptivity in heterogeneous systems, and to exploit multi-core architectures and CGR accelerators, this work proposes the combination of the SPIDER software runtime manager and the data ow-to-hardware MDC design suite for CGR accelerators.
In the last few years, besides the concepts of embedded and interconnected systems, Cyber-Physical Systems (CPS) have become known and studied with interest by the scienti c community. These systems are capable of monitoring and controlling physical elements and consider heterogeneous components that interact with each other in di erent modalities depending on the context in which they operate. Design and maintenance of such systems are extremely complex because of their multidisciplinary nature, the elaborate requirements, the heterogeneity of their components and the continuous communication between physical ? This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 732105. and computing layers. Adaptation according to uncertain events and to changing functional and non-functional requirements is the most important challenge for the developers. In this context, the Cross-layer modEl-based fRamework for multi-oBjective dEsign of Recon gurable systems in unceRtain hybRid envirOnments (CERBERO) H20201 european project aims at developing a design environment for CPS based on two main elements: i) a cross-layer and model-based approach to describe, optimize and analyze the system according to di erent views; and ii) an extended adaptivity of the calculation to the system state as well as to its environment, adaptivity provided by an autonomous recon guration engine. This work is mainly focused on the second CERBERO element, and, in particular, on the study of the ability of the system to dynamically recon gure itself according to its state and to its environment.
Compared to all these approaches considered in Section 2, the proposed framework is focused on providing a combination of the state-of-the-art functionalities within the CERBERO project. To do that, in Section 3, an open-source adaptive management system is proposed, portable over several embedded software systems and heterogeneous CGR hardware accelerators. This type of CGR units are hardware blocks that accelerate a given set of application functionalities switching among them without signi cant recon guration time overheads. Moreover, CGR accelerators can be implemented on both ASIC or FPGA platforms. In order to combine these Processing Elements (PEs) with multi-core architectures, the integration activity between the SPIDER2 data ow-based runtime manager (see Section 2.1) and the MDC3 data ow-to-hardware suite (see Section 2.2) has been conducted. Both tools are based on the data ow Model of Computation (MoC) that can be used to separate temporal and functional problems in hardware design. Moreover, modularity of the data ow representations favors a natural splitting of the computation into di erent blocks, making it possible to automatically map them onto heterogeneous PEs. Thus, the proposed idea is to leverage on a software-hardware design ow to develop and manage data ow-based autonomous recon gurable systems, as requested by the CERBERO model-based approach to system design. Challenges and steps related to the implementation of the integration framework are presented in Section 4. 2
Several tools capable of handling runtime adaptivity have been proposed in
literature. Most approaches concentrate on software management and rely on
existing software frameworks [1, 5{7, 9, 14, 15, 20, 21]. Hardware runtime adaptivity
is managed in [
As mentioned in Section 1, the proposed framework considers a combination of the features provided by the state-of-the-art tools and consists of two existing tools: the SPIDER runtime manager and the MDC suite. 2.1
SPIDER
The Synchronous Parameterized and Interfaced Data ow Embedded Runtime
(SPIDER) is a runtime manager for applications described through
Parameterized and Interfaced Synchronous Data ow (PiSDF) MoC and executed on
heterogeneous multi-core architectures [
Exchange 4 Dataflow
Tokens
Fire Actors 3 ...
1 Schedule Actors
2 Send Order
The Multi-Data ow Composer (MDC) is a toolset for the design and
development of CGR systems based on the Data ow Process Network (DPN) MoC [
MDC o ers also other features that optimize the generated systems and favor
their integration in real environments, such as:
{ a structural pro ler [
SPIDER and MDC show complementary characteristics that motivate their integration. SPIDER provides software scheduling and memory management at runtime for multi-core architectures. However, SPIDER supported processing elements do not include recon gurable hardware blocks and adaptivity is based on an a priori knowledge of several metrics (latency, throughput and memory utilization) evaluated with respect to changes in software parameters. On the contrary, MDC provides a model-to-model compiler capable of merging several data ow applications, as well as a data ow-to-hardware synthesizer that implements CGR systems. Moreover, MDC pro les CGR system con gurations, providing di erent metrics (area, power, frequency) and includes a power manager that o ers clock- and power-gating techniques.
PHYSICAL
PHYSICAL PHYSICAL
Model
System Environment
CYBER
CYBER CYBER Cross Layer (CPSs) System Layer
Computing Layer
Application
Graph
SPIDER
Self-Scheduling Manager Sensors
Multi-ARM SW Monitoring
MDC CGRA Adaptation Engine
HW Monitoring Through PAPI
The proposed framework aims at exploiting the features of SPIDER and
MDC in order to respectively manage software and hardware recon gurability
at runtime. Tool integration is also based on the use of data ow models with
similar properties in order to favour the estimation of metrics such as latency,
throughput and energy. The main idea behind these metrics is to use CGR blocks
as slave processing elements in the target system, and re-schedule these
processing elements from a host processor at runtime using models of the instantaneous
hardware behavior. The adaptation architecture is illustrated in Figure 2. An
application graph, conforming to a PiSDF MoC, is dynamically scheduled by
SPIDER. Depending on the scheduling, a hardware system composed of ARM
cores and CGR accelerators (implemented in Xilinx or Intel modern SoC FPGAs)
performs the computation. Software and hardware monitoring provides feedback
to SPIDER about the current execution of the tasks. Regarding the monitoring,
this feature will be provided through the integration of Papify4, an event-based
performance monitoring tool [
The challenges that this research plan intends to address are summarized as
follows:
i) management of hardware/software adaptivity in systems for which low
energy and time overheads are required;
ii) performance predictability related to the di erent con guration of the
system;
iii) hardware/software fault robustness in architecture composed of
heterogeneous processing elements, such as ARM cores and CGR accelerators.
In order to guarantee fast recon guration and the correct execution of the
application, CGR acceleration and hardware/software monitoring will be considered
respectively. In addition, a strategy based on modeling of architecture and
chosen applications will be used to achieve energy and latency predictability, as
similarly proposed in [
This research plan is part of the activities of the H2020 CERBERO european project, which will be assessed in three di erent use cases among which: planetary exploration (lead by: Thales Alenia Space), smart marine vehicles for ocean monitoring (lead by: AmbieSense), and a smart travelling system for electric vehicles (lead by: TNO in cooperation with Centro Ricerche Fiat). The proposed ow will be used to test applications deriving from the scenarios of the Thales Alenia Space and AmbieSense use cases. To build the proposed ow, the following three steps have been envisioned: { Step 1. Integrate MDC and SPIDER by combining software and hardware adaptation according to variable application parameters; { Step 2. Verify this approach with respect to relevant CERBERO key performance indicators (as latency, throughput and energy); { Step 3. Derive a proof of concept of the proposed approach in the context of
CERBERO project use case scenarios.
The work done so far has been focused on the state-of-the-art adaptation tools and open issues, the study of the tools identi ed for the integration, and the strategies to address the problems described above.
Further developments of the proposed ow will be necessary to improve the decision-making strategy that SPIDER considers for the adaptability of the system. The runtime manager inputs should embed a more detailed description of 4 https://github.com/Papify 5 This activity is planned within the CERBERO project and is currently ongoing. the application to be executed and the model of the architecture on which it has to be performed. Nevertheless, besides managing the known scenarios during the development phase, it would be necessary to take into account also the statistical data related to the experience over a certain period of time, in order to prevent unexpected events at design time. This information should be based on the user interrupts, the external environment and the hardware and software monitors.