-Runtime estimation of power dissipation and performance is crucial in every computing platform. In mobile systems, a special focus is set on energy efficiency in order to achieve the longest possible battery life and at the same time adhering to performance requirements. Powered by heterogeneous SoC's, mobile systems are called to reach an energy efficient state of execution, with a runtime system or scheduler that requires knowledge on the current performance and power dissipation. Today, highly heterogeneous architectures provide many actuators to reach better efficiency, the effect of which is usually unknown at runtime. In this paper, we propose a fast approach to build an energy efficiency model based on hardware performance counters. Our approach obviates the need for power sensors present at the chip level and deals with high numbers of execution modes. In building the energy efficiency model we account for the change in temperature which, as we show, has an impact on the optimal energy efficiency choice. The proposed approach reduces significantly the time to characterize the energy efficiency of a Multiprocessor System-on-Chip (MPSoC) and includes the environment temperature as a variable in determining the energy efficiency. Index Terms-MPSoC, energy efficiency models, platform configuration point, PMC, power models
The past years have seen rapid development in the amount
of data produced, processed and exchanged through
computing systems, ranging from high-end server farms to simple
household devices, and the trend of technology seems to fuel
even more this direction. Based on electricity usage ascribed
to Information and Communication Technology (ICT), it is
predicted that by the end of 2030 this sector will use as much
as 51% of global electricity production [
Therefore one key requirement of such computing
systems is undoubtedly energy efficiency. Basically, this means
that systems should minimize their energy consumption to
complete the required task and achieve a satisfying energy
proportionality [
Workload variability makes the control of energy
expenditure especially difficult in mobile CPUs. Mobile devices
are not the only which require energy efficient solutions,
but also cloud providers need to lower the energy cost of
computations and cooling [
With asymmetric multiprocessing (AMP) architecture there
is a better way to respond to the diversity of applications
present in the mobile environment. We have compute-intensive
applications which need to produce results in real time and
must use fast cores in order to meet the deadlines. On the
other side, background processes that may be memory bound
require little computation and are more suitable to run on
simple cores that achieve better levels of energy efficiency.
Even within a single application, we have different “windows
of activity” which may require varying levels of computing
intensity, e.g. reading, scrolling, responding through different
messages inside a social media application. Recently industry
has moved towards increasing the level of heterogeneity found
inside a single chip. From examples such as ARM big.LITTLE
with two types of cores, to Mediatek tri-cluster MPSoC [
High levels of heterogeneity present in recently
embedded architectures produce an increase in the design space
exploration to find an efficient use of platform actuators. By
increasing the number and type of cores and the number of
voltages and frequency levels for each computing element,
there is an increasing number of operating points on which
the platform may perform. In this scenario making the right
choice for execution could have a tremendous impact on
energy efficiency. Temperature also has a major effect on the
power dissipation of today’s systems [
To manage efficiently the workload scenarios faced by mobile devices, edge devices in IoT, or nano data centers, there is a need to continuously monitor power data in order to fB fs fs fs fs Configurationx fB fB fB fB Configurationt fB fB fB Configurationy fB fB fs fs
fs fs Configurationu Configurationz fs fs
fs fs fs Configurationv Big Cores
Small Cores
MPSoC Fig. 1. Examples of possible platform configuration points in a multicore architecture choose the optimal power and performance trade-off. Unfortunately, most of the hardware platforms today are not equipped with power sensors, which significantly complicates energyefficient management of the system settings.
This paper follows our previous work which experimentally
builds an energy efficiency model based on platform
configuration points, for ARM big.LITTLE architecture [
The contributions of this paper are the following: we propose an approach to characterize the energy efficiency of a hardware platform based on the notion of configuration points. we include environment temperature in the energy efficiency model and show the impact this variable has on the relative efficiency of the points from the model.
less energy consumption.
Exploring the usage of platform actuators for energy
management was studied by different research works. The authors
in [
CMOS technology has been mostly used in MPSoCs due to the fact that has quite good noise immunity and low heat production while the device is in operation mode. Power in these circuits can be divided into two categories: dynamic power and static power. Dynamic power is created by the circuit activity (transistor switching) and is dependent on the usage scenario, clock rates, and I/O activity. Switching power is dissipated during the transistor changing from 0 to 1 and vice versa, the dynamic power is defined as:
Pdynamic =
C
VD2D fclk (1) where C is the load capacitance, VDD is the source voltage, is the activity factor and f is the operating frequency. Static power is dissipated due to the leakage currents on the transistors while they are in the “OFF” mode. The are several sources of the leakage current which are strongly influenced by the chip temperature. The dynamic part of the power dissipated from the chip is modeled by two terms in Equation 2, as a dynamic activity which relates to the active running workloads and the background activity that represents the system processes that run on the background. In Equation 3 the dynamic power is modeled by a single term due to the low power dissipated by background processes in the A7 cluster. Static power is modeled by the third term in Equation 2 and is dependent on temperature and the supply voltage. For the A7 cluster, there is no temperature sensor to monitor, hence the static part is modeled together with the dynamic power dissipation of background activity.
Today embedded systems face a multitude of working scenarios that range from burst in high performance requests, to low power operation modes, going through the need to provide sustainable performance in thermally constrained situations. To do an efficient managing of such a number of use cases the runtime scheduling manager need to have refreshed information about the effect of changing different actuators on the running applications. Thus there is a need for an energy efficiency model which is based on the current runtime power data. The envisioned system diagram is shown in Figure 2, where our work in this paper is focused in providing the platform configuration points database for helping the scheduler decisions in reaching the optimal efficiency level of the running applications.
The work in this paper is based on power models for
mobile CPUs based on hardware program counters (HPC). The
methodology for building such models is adopted from [
We start by building power models for two popular ARM v7a architecture CPU’s, which are ARM Cortex-A7 and ARM Cortex-A15. The micro-architecture limits the number of events which can be sampled at once: 6 counters for A15 and 4 counters for A7 plus the cycle counter. The goal is to search for those events which have the highest correlation with power dissipation and at the same time show the smallest intercorrelation with each other. To have high model stability the predictors should be chosen to keep low levels of multicollinearity in multivariate models. First, is measured the correlation of all available events with the power, then the counters are divided into clusters which include events with high intercorrelation. Then, from each cluster is selected the event which has more impact on the power dissipation but keeping a low Variance Inflation Factor (VIF). The total amount of events for the A7 is 40 and for the A15 in 120, among these are selected 7 for the A15 and 5 for the A7. The events used in the models are general and can be found on most core types used in mobile systems. For each core type, the events are listed on Table I. The power for A15 and A7 is divided in dynamic and static, plus the background power which is related to the operating system activities. (2) (3) The modelled formula for the power dissipation is showed in Equation 2 and 3,
{z dynamic activity nEnVD2Dfclk) + bVD2Dfclk + f (VDD; T )
|BG d{yznamic} | st{aztic } } } |
{z dynamic activity nEnVD2Dfclk) + f (VDD; fclk) static and {BzG dynamic | } where N is the number of events selected, n is the weight given to certain event, En is the number of events per second divided by the frequency (fclk) in MHz, VDD is the operating voltage and T is the temperature of the core.
The power model for the A15 has a thermal compensation term for calculating the static power and background dissipated power when the system is idling (Equation 2). In the power model for A7 the static and background power are included in the second term of Equation 3. This is related to the absence of a thermal monitoring sensor in the A7 cluster. We have calculated four sets of model coefficients for the parameters in each cluster, representing the power with a different number of cores for each CPU type. The model parameters for each core type are given in Tables II and III. In the tables, it is shown the event rate divided by the frequency in MHz, the weight given to each coefficient and the statistical significance. In some model terms, f and V are respectively the operating frequency and voltage of each cluster (Table IV). The event rates are divided by the operating frequency in order to avoid correlation with it in the first term of power equations. The power models need to be obtained only once by running on the target platform a set of embedded representative workloads which we call platform characterization set. After obtaining the power model we compute the energy efficiency table which provides a sort of database of all the possible platform configuration points and the resulting performance, power and energy efficiency values. By having this information the runtime system is able to make decisions about the mapping of a certain application with regard of the performance. If there is a change in the environment temperature above a certain threshold, then the power dissipation can be recomputed and the table is redefined for the new thermal level.
These models are build by running the characterization workload set in each of the operating points of both CPUs. The set contains workloads that test different levels of the microarchitecture and memory subsystem. In part is composed of real applications from the embedded domain, and for the other part synthetic benchmarks designed to stress specific parts of the CPU. Having the power models and by measuring the performance in terms on instructions per second (IPS) we can obtain an energy efficiency model of the platform. The model is presented as a table that lists all the platform configuration points with the energy efficiency levels achieved in terms of instructions per Joule, performance point (instructions per second) and the power dissipation (W). The table is used to decide the optimal configuration point for an application that has defined performance requirements. Once an application is submitted into the system or is resumed by the scheduler, the runtime system can sample the hardware counters in a single frequency level and scans the table to find the optimal configuration point, to run the application, in terms of energy efficiency. In this work, we consider multi-threaded applications, which matches our methodology of achieving optimal levels of energy efficiency by using configuration points that possibly use several cores. In the case where the performance requirement of the application changes, the control logic of the runtime system can select another configuration point that provides the requested performance level and has a high level of energy efficiency. When the temperature of the environment changes above a certain threshold, the power model can be used to recompute the energy efficiency table in accordance with the new temperature conditions. A temperature increase in the outside environment produces an increased level of static power in the CPU, which affects the relative efficiencies of the configurations inside the energy efficiency table. The runtime system can continuously monitor the power usage of the running application in order to not exceed the Thermal Design Power (TDP) of the CPU. By sampling the performance counters of each running application the power model shows the power dissipation at runtime of the running applications, thus the runtime system can make a decision of reducing the power dissipation of certain applications by choosing another configuration point from the system.
The runtime system inputs temperature variations inside the model and can recompute the energy efficiency table by taking into account the new level of static power. The new table needs to be searched for configuration points that satisfy the performance request with the highest level of efficiency. A basic schematic of the proposed approach is given in Figure 2.
To evaluate our approach we used an ODROID XU3 development board from HARDKERNEL. The application processor implements the ARM big.LITTLE architecture with two clusters composed of 4 cores each. The big cluster consists of a high-performance Cortex-A15 quad-core block, and a low power Cortex-A7 quad-core CPU. The board description is complete with a Mali-T628 GPU and 2GB LPDDR3 of memory. The board contains 4 current sensors that offer the possibility to measure power dissipation in four different domains: big cluster (A15), LITTLE cluster (A7), GPU and memory. Besides this, the board contains 4 temperature sensors for the cores in the big cluster and one temperature sensor for the GPU. The characteristics of the hardware can be found in Table IV.
To build the power model we used a set of benchmarks
from different application domains. We call the training set as
the platform characterization workloads. In the platform
characterization set we include a sequence of 76 workloads which
consists of a collection of synthetic and real world applications
from Roy Longbottom [
The choice of the workload set is based on the idea of allinclusiveness of applications that characterize the embedded systems domain.
Experiments were conducted in different environments to account for the outside temperature change in the SoC power dissipation. The goal here is to evaluate the change in the energy efficiency table in accordance with temperature. For the first environment, the board fan is running with 100% speed with the system located in a highly refrigerated environment. In the second case, the board is working with the fan disabled in a normal outside temperature to account for a high temperature outside the environment. In the third case, the board is working with the fan always on in a normal environment, to justify the middle case. In Table, VI on Section V we will show the result of the energy efficiency table computed in different environments.
By using the power and performance models defined
previously we are able to derive an energy efficiency model which
is based on platform configuration points. In Figure 3 we show
the efficiency of all configuration points from the model. Each
point describes a single configuration that provides a certain
level of performance in terms of instructions per second and
energy efficiency. By going towards high levels of performance
we notice a decrease in the density of the points. This means
that fewer options for achieving good energy efficiency levels.
The list of configurations is organized as an energy efficiency
table that lists all possible configuration points with their
efficiency and performance. An example of the table derived
from the workloads in the training set of the power model is
shown in Table VII. By searching inside the table we find
several sets of configuration points that provide the same
performance but with different energy efficiency levels, some
of the sets are shown in Figure 4. First usage of the table
would be the one for choosing the optimal configuration point
based on a certain requirement for the performance level. As it
is shown by Figure 4, it is possible to gain in terms of energy
efficiency if we make the right choice for the configuration
point. As a second objective of our work, we wanted to test
the effect of temperature on the relative energy efficiency of
configuration points in the model. For testing thermal effects
on the efficiency model, we choose to run a testing application
with the system located in different environments. We run
Basicmath application from the ParMiBench suite [
The top rows of the energy efficiency table for different temperature environments are shown in Table VI. Different temperature levels produce different order of configuration points and efficiency levels achieved. This shows that there is a need to change the platform configuration point when the temperature changes significantly, in order to keep the high levels of energy efficiency.
In Figure 5 we show a possible runtime scenario. We are running Basicmath test application with a required level of performance such as e.g. 1,61E+9 inst/s in a system with a temperature t1, according to the model the optimal configuration point for this performance level is composed by 2a7@400MHz + 4a15@500MHz. In the case, the temperature increases to t2, then the efficiency of that configuration point decreases and thus we need to reconfigure with the new table that shows that we should execute the application by using the following configuration 4a7@700MHz + 4a15@200MHz. Another example is shown with the performance requirement of 3,27E+9 inst/s, where again there is a need for reconfiguration in order to keep high levels of energy efficiency.
The change in the environment temperature of the system (from “cold” to “hot”) produces large differences in the energy efficiency levels that the model defines as an optimal configuration point for the required performance. By looking at the first 100 highly energy efficient configurations in the energy efficiency table, we find few test cases, whereby changing the configuration point when the system temperature changes the gain in terms of energy efficiency is up to 33%. By searching for new target reconfiguration points we account for the same performance or 5% bigger. An interesting observation can be noticed in Figure 3 where all points are plotted in the energy efficiency and performance graph. If we take the points from the upper outer layer of the scatter plot we have a situation like in Figure 6. Those points show the configurations with the optimal energy efficiency for a certain level of performance at a defined temperature. Or otherwise, we can think of the graph as the result of scanning the model from the lowest performance point and keeping only those points which have higher performance and the highest possible level of energy efficiency. As a further validation of our approach, we measure in percentage the difference between the predicted power dissipation and the measured power in configuration points with high levels of energy efficiency. The results are shown in Figure 7, where we notice the highest error is 2,82%. We measure the model errors in configurations that provide the highest levels of energy efficiency for different performance levels. These are more intriguing configuration points, which give the best of the platform’s energy efficiency. Knowing that most of the time these points will be used as configuration options, having a low error rate from the model is very useful.
In this work, we present an approach for building an energy efficiency model which is based on platform configuration points. The target of the approach are heterogeneous platforms which are continuously increasing the depth of heterogeneity. The model is based on hardware performance counters which are widely available in today’s CPU architectures. The set of workloads for building the model is representative of the embedded domain which has shown to be more critical to the energy efficient application execution. But also, the training set, in inclusive of the IoT world. The novelty of this approach compared to previous works is that it doesn’t necessarily need power sensors for measuring the power dissipation in each configuration point, but by sampling the counters on one configuration point we can characterize the efficiency of other configuration points. From all the points in the model, we show that less than 1% of them (see points in Figure 7) represent the highest levels of energy efficiency possible, in all the performance spectrum offered by the platform. Also, we include the environment temperature as a variable for defining the need for application reconfiguration. As we show by the tests if the temperature changes, by reconfiguring the application execution we can gain up to 33% in terms of energy efficiency.