The Drift Tube (DT) system is the primary detector in the barrel region of the CMS experiment dedicated to the measurement of muon tracks. The signals from about 172 000 DT cells must be fast and synchronously acquired to deliver the information about hits. In the context of the increasing luminosity of the LHC, in preparation for Phase 2, the DT system is being upgraded. The main focus of this upgrade is the development of a new generation of read-out electronics based on FPGA technology. The new on-chamber electronics will provide higher acquisition rates, increased radiation tolerance, and improved flexibility of the trigger settings for the DT system. The DT chambers will be equipped, depending on chamber type, with 3 to 5 unified boards called On-Board electronics for Drift Tubes (OBDTs). Along with better read-out characteristics, the OBDTs ensure fewer intermediate elements in the read-out chain. This contribution presents an overview of the new read-out chain and OBDT architecture.
During Long Shutdown 2 (LS 2) of the Large Hadron Collider (LHC), many upgrade activities on different LHC sites are planned. In the barrel region of the Compact Muon Solenoid experiment (CMS), the muon detection system is composed of 250 Drift-Tube (DT) chambers. Each of the DT chambers consists of a number of oblong gas detector cells. Depending on the location, the particular DT chamber can have a different size and therefore have a different number of the gas cells, which can vary between 700 and 1200 per DT chamber. Each cell is operating as a classic gas detector filled with a gas mixture (Ar:CO2 85%:15%) and equipped with high-voltage electrodes. The DT chamber also contains the front-end circuits to capture the hit events as a muon flies through a particular cell. The electric output of a front-end circuit of a DT cell is a Low-Voltage Differential Signal (LVDS) pulse. This pulse is transferred through a pair of wires to the DT chamber’s acquisition electronics. It is important to synchronously acquire the hit information from all cells of all DT chambers in order to be able to reconstruct the track information properly. For this purpose, one of the ends of each DT chamber is equipped with a compartment, referred to as a DT minicrate. The minicrate contains the first level read-out electronics which digitizes the exact hit times from all front-end circuits of all cells of the DT chamber. The read-out electronics of the minicrate is the beginning of a read-out chain. Currently this read-out chain includes a number of components and ends on the other side with specialized boards stacked into the Micro Telecommunications Computing Architecture (µTCA) crates. These crates are located in the underground service cavern (USC) of CMS. The read-out chain is the focus of the DT upgrade activities. No upgrade is planned for the front-end circuits of the DT cells. The subjects considered below are the structure of the read-out chain and, in particular, the new electronics of the DT minicrate that performs the read-out of the front-end circuits.
The read-out chain which is in operation till the end of Phase 1 is often referred to as the legacy chain. One can subdivide the legacy chain into the following hierarchical stages with their respective components: • • •
Minicrate Read-Out Boards (ROBs) [
Copper to Optic Fiber converters (CuOF) [
• •
The new read-out chain contains two stages:
integrated FPGA based solution for fast parallel digitization of the DT chamber front ends. The TDC blocks, which were previously implemented in the dedicated ASICs, are now implemented directly in the FPGA of the OBDT. Together with read-out routines, the FPGA chip drives the uplink communication of the OBDT. This communication includes streaming of the hit data as well as transfer of clock data and slow control data. The communication links connected to the OBDT are fiberglass based. This makes the use of any intermediate components (like CuOFs previously) unnecessary. A more detailed description of the OBDT and its components is given in section 3.
AB7 and MoCo boards: these are slot boards hosted inside particular µTCA crates. Each AB7 board is a back-end system that handles the hit data streams from 3 to 5 OBDTs installed on a particular DT chamber. Uplink connection from OBDTs is provided in the way, that the complete data stream of all OBDTs of one DT chamber is covered by a single AB7 board. The routines for extracting the trigger primitives are implemented in the firmware of the AB7. The AB7 then sends data about the recognized trigger patterns to the BMTF. The AB7 also transfers the filtered hit data to the cDAQ system. The MoCo board implements the slowcontrol communication as well as providing the clocking data packages for up to 12 OBDTs. Both the AB7 and MoCo boards are based on the same TM7 hardware platform. This platform is identical to the one used by the back-end boards in the legacy chain (i.e. by µROS and TwinMUX boards). Particular specialization of a TM7 board is provided entirely by the firmware. The universality of the back-end boards at the hardware level contributes to the better serviceability.
The reduced number of electronic units in the UXC ensures higher reliability of the whole read-out chain. The second architectural advantage is the whole trigger logic moves completely to the back-end AB7 boards located in the USC. Since each of the AB7 boards acquires the whole stream of hit data of one particular chamber, the trigger primitives are now recognized based on the whole scope of cells within a particular DT chamber. This step also ensures a better maintenance of the read-out chain because the USC is accessible during the run time of the LHC.
The OBDT is an FPGA based board for the read out of the DT chamber’s front-end circuits.
Since the OBDT is the only unit of the read-out chain which will reside in the UXC, radiation tolerant
components were selected for the design of this board. The central part of the OBDT is the FPGA
PolarFire MPF300T [
This precise time acquisition is performed by the TDC blocks, which are implemented inside
the FPGA. The basic functional blocks of TDCs are the deserializers commonly present in modern
FPGAs. In particular, for the PolarFire family, the deserializers used are called SERDES blocks [
Next to the FPGA, is the GBTx [
A set of 14 OBDT prototypes have been produced for a series of tests described below. One of the assembled OBDT prototypes is shown in Figure 3. A subset of 12 OBDTs are mounted on the neighboring DT chambers of the second wheel of the CMS detector (positive side). Since all the OBDTs are in the same wheel-sector, the series of tests is often referred to as a Slice Test. The OBDTs participating in the slice tests are subdivided into two groups: • •
Group for integration tests: 6 OBDTs were mounted in the minicrate compartments of the MB1 and MB2 DT chambers. All possible integration activities are provided for these boards in order to test the final configuration of the cooling, mechanics, and cabling. A further important aspect here is to obtain the understanding of time and material resources needed for the replacement of the considered components.
Group for read-out validation tests: 6 OBDTs were mounted on the MB3 (2 boards) and MB4 (4 boards) DT chambers. The OBDTs of this group are working in parallel with the legacy chain. This is made possible with help of additional splitter boards, inserted directly after the front-end circuits. These splitters provide analog splitting of all front-end signals, ensuring that the signals from every front-end channel can be simultaneously acquired by both legacy and Phase 2 read-out chains. This is needed to validate the correctness of the hit data, acquired by the new read-out chain. The plot in Figure 4 demonstrates the time coincidence of the registered hits acquired by both Phase 2 and legacy read-out chains.
A new read-out chain was developed for the CMS DT system in preparation for LHC Phase 2. The new read-out chain offers improved architecture using fewer standalone functional blocks. The design of the new on-chamber electronics (OBDT) ensures a precision for registering the hit events below 1 ns. The first set of OBDT prototypes was produced. Ongoing tests show the expected performance of the whole read-out chain. The final version of the DT chamber electronics will be developed based on the considered OBDT prototype.