The paper gives a brief view on the process of analysis and adapting formal description of the current version of the VHDL language, described by VHDL 1076-2002standard. The work searchesthe possibility to build the effective syntax analyser of the entire language by using automatic tools for parsers generation.
VHDL is the acronym for VHSIC Hardware Description Language. It is a language that can be used to describe the structure of digital circuits or even behavior of the hardware designat the various levelsof abstraction. It is a powerful language,but always restricted by the capabilities and aim of used tools.
The fundamental motivation for the construction of the complete VHDL parser is to be able to analyzearbitrary VHDL sourcecode without dependency on the sourcetool. In past, there were introduced some methods (..S. [a]), but only for very old version of VHDL standard. The concrete utilization is in automatic or semi-automatic VHDL-based modules generation that representsthe user components design.
The VF{DL-2002 standard (see [
The forrn of the extension is given by italicized prefix of the nonterminal's name.l'he prefix carriescrucialsernanticinforrnation.For example,nonterminals type-name and subtypename are both syntactically equivalent to name, but carry the semantic information about the context in which they were derived. In this paper, call this extension semant'iccondi,t'ion.
Semantic conditions are unusual in parsing theory (see [
In the case of our fundamental research,the existing EBNF description of the VHDL-2002 languagehasbeentranscripted into the input grammar for the Bison tool. The semantic conditions were left unchangedin this step.
The second part of the transformation had to separate the syntax part of the description from the semantic information. All nonterminals with italicized prefixeswere renamedonto original nameswithout theseprefixes.In this moment the grammar stopped to remember the context of transformed nonterminals, this context has to be added later.
The context had previously influencedthe selectionprocessof currently used rule when deriving sentential form by parsing the input VHDL source. The consequenceis that the transformed grammar became ambiguous due arisen reduce/reduce conflicts. The basic task is to eliminate the ambiguity in the grammar and simultaneously preserve the ability of the grammar to generate the entire VHDL-2002. The grammar constructed by standard rewriting of the EBNF contains 743 productions, 78 shif[/reduce conflicts and foremostly 579 reduce/reduceconflicts.
The huge ambiguity in VHDL grammar is solved in two independent ways. The former usesconditional building of syntax tree in the processof syntax analysis. For making decisionabout the next advanceof its production there is used some semantic knowledge acquired by the analysis of already processedsource code. The latter way usesconsecutivemerging of all corresponding conflicting syntactic categoriesinto one. This way consecutivelyeliminates ambiguities but it alsoremovesthe original semantic dependenciesestablishedin the VHDL-2002 standard.
This method of semantic conditions elimination utilizes inserting of new auxiliary terminal symbols to the input of the parser.It means that the output of the lexical analyser is not directly connectedto the input of the parser but there is an A Noteon theParsingof CompleteVHDL-2002 auxiliary generator that they are connectedthrough. This generator is tightly bound to the semantic analyser and syntactic analyser and during analysis it inserts auxiliary terminals at the right placesin the input streani of tokens (simplified schemaof such analyseris shown on the figure 1). The binding between auxiliary generator and parser has to be created as special semantic actions in the parser code.
Legend: ----)- Common Dataflow
- - L- Auxiliary Dataflow
The auxiliary terrninals are inserted in the grammar immediately after conflicting (really only after conflicting not all semantically conditioned) nonterminals originalll' containing semantic conditions. Each inserted terminal has its name deduced from this semantic condition. Consequentlyduring analysis, if it is detected such a nonterminal is in progress,the auxiliary terminal generator is activated. The decision whether insert an appropriate auxiliary terminal or not is basedon the information provided by the semantic analyser.For example, there is shorvna solution of conflicts in part of VHDL-2002 grammar containing nonterminals type-rame and sub typename in the Example l.
Erample 1. Solution of the typical reduce/reduceconflict in VHDL grammar. The symbols -TYPE-and -SUBTYPEa-re the new auxiliary terminals. subtype-declaration : SUBTYPE1d IS subtype_lndicatlon , ;, subtype-indication => . .. :+ type_mark type-mark : nane _TYPE_
I name -SUBTYPEreport-statement : REP0RTexpression t . tt e x p r e s s i o n + . . . + prinary primary : name ; U
There was eliminated all the reduce/reduceconflicts in the VHDL grammar using this rnethod. But prnctical usability of this method has not been yet verified becauseit needs a working basic semantic analyser providing sufficient information to the auxiliary generator. However, the semantic analysis was not the main focus of this researchphase and will be handled in the future.
This method seemsto be a good candidatefor the constructionof a complete analyser of VHDL, becauseit does not modify original form of VHDL grammar. Therefore, it may be possible to use it as a base of an universal tool enabling both simulation and synthesiswithout the need of separateworking with some VHDL code for simulationsand another VHDL code for svnthesis. 3.2
It is certainly the best solution to use an unambiguous grammar as a base of a parser. Thus, we are working on an unambiguous version of VHDL grammar. Currently, we have solved about 500 reduce/reduce conflicts and 76 remain for future work. As a result of this work, there should be an universally usableVHDL grammar suitable as a baseof standalonesyntactic analyserof VHDL. Because of the big number of modificationsin the grammar structure, it is supposedt.o be too awkward as a baseof completeVHDL analyseror synthesistool.
As in the first approach,here is one big problem too. The grammar is too complex and eliminating of conflicts is very hard task. In addition, it is not known whether it is possibleto describeentire VHDL using LALR grammar or not. There are sonle additionat possibilities like for example generalized LR parsing provided by Bisorr.but tiresepowerful analysershave generally very poor performancein caseof complex languageswith many conflicts. 4
VHDL is a very complex language. It contains a number of semantic enhancetnents in its standard syntax definition. From this fact follows that the process of the universal VHDL parser creation is very hard task. Currently, we havi: found some \^,'ayswhich may tend to achievethis goal. These ways were briefly describedin this paper same as someopen problems.
This work has been supported by MinistrV of Education, Youth and,Sports of the CzechRepublic arant hISIV'IT2C06008 "Vi,rtual Laboratory of Microprocessor TechnologyA ppli,cat,ion."