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  <front>
    <journal-meta />
    <article-meta>
      <title-group>
        <article-title>Checking MTL Properties of Timed Automata with Dense Time using Satisfiability Modulo Theories (Extended abstract)</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <string-name>Agnieszka M. Zbrzezny</string-name>
          <xref ref-type="aff" rid="aff0">0</xref>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Andrzej Zbrzezny</string-name>
          <xref ref-type="aff" rid="aff1">1</xref>
        </contrib>
        <aff id="aff0">
          <label>0</label>
          <institution>Faculty of Mathematics and Computer Science, University of Warmia and Mazury in Olsztyn</institution>
          ,
          <country country="PL">Poland</country>
        </aff>
        <aff id="aff1">
          <label>1</label>
          <institution>Institute of Mathematics and Computer Science, Jan Długosz University in Cze ̧stochowa</institution>
          ,
          <country country="PL">Poland</country>
        </aff>
      </contrib-group>
      <abstract>
        <p>We investigate a new SMT-based bounded model checking (BMC) method for the existential part of Metric Temporal Logic (MTL). The MTL logic is interpreted over linear dense infinite time models generated by timed automata with dense time. We implemented the new SMT-based bounded model checking technique for MTL and as a case study we applied the technique to the analysis of the Timed Generic Pipeline Paradigm and Timed Train Controller System, both modelled by a network of timed automata.</p>
      </abstract>
    </article-meta>
  </front>
  <body>
    <sec id="sec-1">
      <title>1 Introduction</title>
      <p>
        Timed automata [
        <xref ref-type="bibr" rid="ref2">2</xref>
        ] are very convenient for modelling and reasoning about real-time
systems: they combine a powerful formalism with advanced expressiveness and
efficient algorithmic and tool support. The timed automata formalism is now applied to
the analysis of timing analysis of software and asynchronous circuits [
        <xref ref-type="bibr" rid="ref12">12</xref>
        ] and
realtime control programs [
        <xref ref-type="bibr" rid="ref13">13</xref>
        ]. Timed automata technology was also used to analysis of
numerous real-time communication protocols [
        <xref ref-type="bibr" rid="ref20">20</xref>
        ].
      </p>
      <p>
        Timed automata (TA) are adequate to represent systems, but not that much for
representing properties of systems3. Temporal logics are a well known framework in the
field of specification and verification of computer systems [
        <xref ref-type="bibr" rid="ref18">18</xref>
        ]. Linear Temporal Logic
(LTL) allows to express properties about each individual execution of a system, such
as the fact that any occurrence of a problem eventually triggers the alarm. Real-time
constraints have naturally been added to temporal logics [
        <xref ref-type="bibr" rid="ref1 ref16">16, 1</xref>
        ] at the beginning of the
90s. The resulting logics allow to express e.g. that any occurrence of a problem in a
system will trigger the alarm within at most 5 time units.
      </p>
      <p>
        Metric Temporal Logic (MTL) [
        <xref ref-type="bibr" rid="ref16">16</xref>
        ] was discussed in the literature e.g on the
verification of real-time systems [
        <xref ref-type="bibr" rid="ref11 ref14 ref19 ref22 ref7">14, 11, 22, 19, 7</xref>
        ]. MTL extends the until and globally
3 Assume that one TA represents a system and the second TA represents a property of the
system. We would like to check if TA representing the system satisfies the property. This
problem is unfortunately undecidable for timed automata.
operators of classical temporal logic with an interval which specifies the time interval
within which the formula must be satisfied. The MTL logic has traditionally been
interpreted in two ways: the pointwise and the continuous semantics. In this paper we are
focused on the pointwise version. The temporal assertions are interpreted only at time
points where an action happens in the observed timed behaviour of a system.
      </p>
      <p>
        Bounded model checking [
        <xref ref-type="bibr" rid="ref17 ref8 ref9">8, 9, 17</xref>
        ] (BMC) is one of the symbolic model checking
technique designed for finding witnesses for existential properties or counterexamples
for universal properties. Its main idea is to consider a model reduced to a specific depth.
The method works by mapping a bounded model checking problem to the Boolean
satisfiability problem (SAT) or to satisfiability modulo theories problem (SMT).
      </p>
      <p>
        The satisfiability and model checking problems for MTL are undecidable over the
interval-based semantics [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]. This has led to consider various restrictions on MTL to
recover decidability [
        <xref ref-type="bibr" rid="ref21 ref22 ref3">21, 22, 3</xref>
        ]. The main steps of our new method for MTL and timed
automata with dense time can be described as follows:
1. the timed model (infinite) is reduced to a finite model,
2. the MTL formula is translated to LTLq formula [
        <xref ref-type="bibr" rid="ref24 ref25">24, 25</xref>
        ],
3. since the interval modalities in MTL appear as literals in LTLq formula, the
existential properties are reduced to a satisfiability modulo theories problem (SMT).
      </p>
      <p>We evaluate the new BMC method experimentally by means of a timed generic
pipeline paradigm (TGPP) and timed train controller system, which are modelled by a
network of timed automata with dense time.
2</p>
    </sec>
    <sec id="sec-2">
      <title>Timed Automata</title>
      <p>The model of timed automata has been defined in the 90s by Alur and Dill as a model
for representing systems with real-time constraints. A timed automaton is basically a
finite automaton which manipulates finitely many variables called clocks.</p>
      <p>We assume a finite set X = fx0; : : : ; xn 1g of variables, called clocks. A clock
valuation is a total function v : X 7! IR that assigns to each clock x a non-negative
real value v(x). The set of all the clock valuations is denoted by IRjX j. For X X , the
valuation v0 = v[X := 0] is defined as: 8x 2 X, v0(x) = 0 and 8x 2 X n X, v0(x) =
v(x). For 2 IR, v + denotes the valuation v00 such that 8x 2 X ; v00(x) = v(x) + .
Let x 2 X , c 2 IN, and 2 f&lt;; 6; =; &gt;; &gt;g. A guard over X is a finite conjunction
of expressions of the form x c. We denote by C(X ) the set of guards over X . A clock
valuation v satisfies a clock guard cc, written as v j= cc, iff cc evaluates to true using the
clock values given by the valuation v.</p>
      <p>Definition 1. A timed automaton is a tuple A = (Act; Loc; `0; T; X ; Inv; AP; V ), where
– Act is a finite set of actions,
– Loc is a finite set of locations,
– `0 2 Loc is an initial location,
– T Loc Act C(X ) 2X
– X is a finite set of clocks,
– Inv : Loc 7! C(X ) is a state invariant function,</p>
      <p>Loc is a transition relation,
– AP is a set of atomic proposition, and
– V : Loc 7! 2AP is a valuation function assigning to each location a set of atomic
propositions true in this location.</p>
      <p>Each element t 2 T is denoted by ` ;c!c;X `0, and it represents a transition from location
` to location `0 on the input action . X X is the set of the clocks to be reset with
this transition, and cc 2 C(X ) is the enabling condition for t.
2.1</p>
      <sec id="sec-2-1">
        <title>Concrete model</title>
        <p>The semantics of the timed automaton is defined by associating a transition system with
it, which we call a concrete model.</p>
        <p>Definition 2. Let A = (Act; Loc; `0; T ; X ; I nv; AP ; V ) a timed automaton, and v0a
clock valuation such that 8x 2 X , v0(x) = 0.</p>
        <p>A concrete model for A is a tuple MA = (Q; q0; !; V ), where
– Q = Loc IRn s a set of the concrete states,
– q0 = (`0; v0) is the initial state,
– ! Q Q is a total binary relation on Q defined by action and time transitions
as follows. For a 2 Act and 2 IR+,
1. Action transition: : (`; v) a! (`0; v0) iff there is a transition ` a;c!c;X `0 2 T
such that v j= cc ^ I nv(`) and v0 = v[X := 0] and v0 j= I nv(`0),
2. Time transition: (`; v) ! (`; v + ) iff v j= I nv(`) and v + j= I nv(`).
– V : Q 7! 2AP is a valuation function such that V ((`; v)) = V (`) for each state
(`; v) 2 Q.</p>
        <p>A run</p>
        <p>in a concrete model for the timed automata A is a infinite sequence of
concrete states q0 0!;a0 q1 1!;a1 q2 2!;a2 : : : such that qi 2 Q, ai 2 Act and i 2 IR+,
for all i 2 IN. An assumption that i 2 IR+ implies that runs are strongly monotonic.
This is because the definition of the run does not permit two consecutive actions to be
performed one after the other, i.e., between each two actions some time must pass.
3</p>
      </sec>
    </sec>
    <sec id="sec-3">
      <title>MTL logic</title>
      <p>
        MTL logic [
        <xref ref-type="bibr" rid="ref16">16</xref>
        ] (metric LTL) is a timed temporal logic with interval operators. It has
received much attention in the literature on the verification of real-time systems. MTL
can express many time constraints. For example we can express a system property: if a
system is in the state q, than it will be in the state q0 exactly 3 time units later.
Syntax Let p 2 AP be a propositional variable and I be an interval in IN of the form
[a; b) or [a; 1), where a; b 2 IN and a &lt; b. The MTL logic in release positive normal
form is defined in the following way:
:= true j false j p j :p j
^
j
_
j
      </p>
      <p>Intuitively, UI and GI are the operators for, respectively, bounded until and bounded
always and they are ridden as, respectively, „until in the interval I” and „always in the
interval I”. The operators FI and RI are defined in the standard way:</p>
      <p>FI
d=f true UI</p>
      <p>RI
df
= GI _</p>
      <p>UI(
_ ).</p>
      <p>
        Semantics Over dense time the logic has traditionally been interpreted in either of two
ways which have come to be known as the “pointwise” and the “continuous”
semantics [
        <xref ref-type="bibr" rid="ref10">10</xref>
        ]. In the pointwise approach temporal assertions are interpreted only at time
points where action happens in the observed timed behaviour of a system. In the
continuous one is allowed to assert formulae at arbitrary time points between actions as
well.
      </p>
      <p>In the presented method we use the pointwise semantics.</p>
      <p>
        Let A be a time automata, MA = (Q; q0; !; V) be a concrete model for the timed
automata A, : q0 !0 q00 a!0 q1 !1 q10 a!1 q2 !2 q20 a!2 : : : be a run in A, which
can be written in the shorter way: : q0 0!;a0 q1 1!;a1 q2 2!;a2 : : :. Each of the runs
determines the path : q0; q00; q1; q10; q2; q20 : : : in an unambiguous way. Given a run
one can define a function : IN 7! IR+ such that, for all the position j &gt; 0, (j) is
a sum of all the time transitions along the run till the position j. For all j &gt; m, the
function (j) returns the value of the global time (in [
        <xref ref-type="bibr" rid="ref10">10</xref>
        ] called „duration”).
      </p>
      <p>To make the definition more clear we use a notation ( ; m)j=EMTL' instead of
M; ( ; m)j=EMTL', for each MTL formula '.</p>
      <p>Definition 3. Let and be MTL formulae. The satisfaction relation j=EMTL, which
indicates truth of an MTL formula in the concrete model MA along a path starting
at position m 2 IN, is defined inductively as follows:
( ; m) j=EMTL true,
( ; m) 6 j=EMTL false,
( ; m) j=EMTL p iff p 2 V( (m)),
( ; m) j=EMTL :p iff p 62 V( (m)),
( ; m) j=EMTL ^ iff ( ; m) j=EMTL
( ; m) j=EMTL _ iff ( ; m) j=EMTL
( ; m) j=EMTL UI iff (9j m)( (j)
and (8m 6 j0 &lt; j)( ; m + j0) j=EMTL ),
( ; m)j=EMTL GI iff (8j m)( (j)
and ( ; m) j=EMTL ,
or ( ; m) j=EMTL ,</p>
      <p>(m) 2 I and ( ; m + j) j=EMTL
(m) 2 I implies ( ; m + j) j=EMTL ).</p>
      <p>As ( ; 0) = , we shall write MA; j=EMTL ' for MA; ( ; 0) j=EMTL '.
An MTL formula ' is existentially valid in the model MA, denoted MA j=EMTL E',
if, and only if MA; j=EMTL ' for some path starting in the initial state of MA.
Determining whether an MTL formula ' is existentially valid in a given model is called
an existential model checking problem.
4</p>
    </sec>
    <sec id="sec-4">
      <title>SMT-based bounded model checking</title>
      <p>
        The verification method presented in this paper is based on the translation of MTL
formulae to LTLq formulae defined in [
        <xref ref-type="bibr" rid="ref24 ref25">24, 25</xref>
        ]. We do not report on this step here in
detail, since it requires introducing the huge mathematical machinery, but in fact it can
be done in a way similar to the one presented in [
        <xref ref-type="bibr" rid="ref24">24</xref>
        ]. However, this will be provided in
the full version of the paper. We refer the reader to the chapter 4 of the thesis [
        <xref ref-type="bibr" rid="ref24">24</xref>
        ] for
details.
      </p>
      <p>
        The SMT-based bounded model checking can be described in the following steps:
1. Since the concrete model is infinite we have to abstract the model to be able to
applied bounded model checking technique. It is a well-known technique [
        <xref ref-type="bibr" rid="ref15 ref4">15, 4</xref>
        ].
2. We use the EMTL semantics in the abstract model [
        <xref ref-type="bibr" rid="ref24">24</xref>
        ] and translate the EMTL
formula into an LTLq formula.
3. The next step is standard. It consists of a translation of the transition relation in
the depth k in the abstract model and the LTLq formula into satisfiability modulo
theories problem. The difference between the BMC method for classic LTL and our
method lies in encoding of a finite prefix ( l (0); l (1); : : :).
4. After the translation to SMT, the SMT-solveer checkes the satisfiability of the LTLq
formula in the abstract model.
5
      </p>
    </sec>
    <sec id="sec-5">
      <title>Experimental results</title>
      <p>
        In this section we experimentally evaluate the performance of our new translation.
We have conducted the experiments using the slightly modified timed generic pipeline
paradigm (TGPP) and timed train controller system (TTCS) [
        <xref ref-type="bibr" rid="ref23">23</xref>
        ].
5.1
      </p>
      <sec id="sec-5-1">
        <title>Timed Generic Pipeline Paradigm</title>
        <p>The Timed Generic Pipeline Paradigm (TGPP) timed automata model shown in Figure 1
consists of a Producer producing data within the certain time interval ([a; b]) or being
inactive, a Consumer receiving data within the certain time interval ([c; d]) or being
inactive within the certain time interval ([g; h]), and a chain of n intermediate Nodes
which can be ready for receiving data within the certain time interval ([c; d]), processing
data within the certain time interval ([e; f ]) or sending data. We assume that a = c =
e = g = 1 and b = d = f = h = 2 n + 2, where n represents a number of nodes in
the TGPP.</p>
        <p>
          To compare our experimental results with [
          <xref ref-type="bibr" rid="ref23">23</xref>
          ], we have tested the TGPP timed
automata model, scaled in the number of intermediate nodes on the following MTL
formulae that existentially hold in the model of TGPP (n is the number of nodes):
– '1 = F[0;2 n+3)(ConsReceived). It expresses that Consumer receives the data in
at most 2 n + 3 time units.
– '2 = G[0;2 n+2)(ConsReady). It states that the Consumer is always forced to
receive the data in 2 n + 2 time units.
– '3 = G[0;1)(P rodReady _ConsReady). It states that always either the Producer
has sent the data or the Consumer has received the data.
– '4 = F[0;2 n+3)(G[0;1)(P rodSend _ ConsReceived)). It states that eventually
in time less then 2 n + 3 it is always the case that the Producer is ready to send the
data or the Consumer has received the data.
– '5 = G[0;1)(F[0;2 n+3)(ConsReceived)). It states that the Consumer infinitely
often is receiving the data in time less then 2 n + 3.
        </p>
        <p>The Timed Train Controller System (also known as Fischer’s mutual exclusion
protocol) consists of n (for n 2) trains T1; : : : ; Tn, each one using its own circular track
for travelling in one direction and containing its own clock xi, together with controller
C used to coordinate the access of trains to the tunnel through which all trains have to
pass at certain point. There is only one track in the tunnel, so trains arriving from each
direction cannot use it in this same time. There are signals on both sides of the tunnel,
which can be either red or green. All trains notify the controller when they request
entry to the tunnel or when they leave the tunnel. The controller controls the colour of
the displayed signal, and the behaviour of the scenario depends on the values and
( makes it incorrect - the mutual exclusion does not hold).</p>
        <p>Controller C has n + 1 states, denoting that all trains are away (state 0), and the
numbers of trains, i.e., 1; : : : ; n. Controller C is initially at state 0. The action Starti
of train Ti denotes the passage from state away to the state where the train wishes to
obtain access to the tunnel. This is allowed only if controller C is in state 0. Similarly,
train Ti synchronises with controller C on action approachi, which denotes setting C
to state i, as well as outi, which denotes setting C to state 0. Finally, action ini denotes
the entering of train Ti into the tunnel.</p>
        <p>–
–
–
1 = F[0;7)(Win=11 Wn</p>
        <p>j=i+1(tunneli ^tunnelj )). It states that the mutual exclusion
property is violated, i.e. for some path some two trains are in the tunnel at the same
time. The formula is existentially valid in the model if and only if .
2 = G[0;1)(F[0;9)(Wn</p>
        <p>i=1(tunneli))). It states that always eventually some of the
trains enters the tunnel. The formula is existentially valid in the model regardless
of the values of and .</p>
        <p>3 = F[0;1)(Win=1(tunneli)). It states that eventually all the trains are in the
tunnel. The formula is existentially valid in the model if ndonlyif .
5.3</p>
      </sec>
      <sec id="sec-5-2">
        <title>Performance evaluation</title>
        <p>We have performed our experimental results on a computer equipped with I7-5500U
processor, 12 GB of RAM, and the operating system Linux with the kernel 5.2.9. Our
SMT-based BMC algorithm is implemented as standalone programs written in the
programming language C++. We used the state of the art SMT-solver Z3 (program version
8.4.5).</p>
      </sec>
      <sec id="sec-5-3">
        <title>TGPP</title>
        <p>The number of considered k-paths (fk) for the translation is always equal to 1. The
length of the witness for the formula '1 is equal to 4 (n + 1) ; for the formula '2 is
equal to 8 n + 6; for the formula '3 and is equal to 8 n + 6; for the formula '4 is
equal to 8 n + 15; for the formula '5 is equal to 8 n + 6.</p>
        <p>The experimental results presented on the Fig. 3 show total time usage. We can
observe that the SMT-based method is sensitive to scaling up the size of the
benchmarks. For more complicated formulae time usage grows very fast with the size of the
benchmark.</p>
        <p>The maximum memory usage for all the formulae showed on the Fig. 4 is not very
big. The biggest memory usage was for the formula '5 and it amounts 375 MB.</p>
        <p>Fig. 5 shows time usage for bounded model checking algorithm ( translation of the
model and the formula to SMT format) and for the SMT-solver. We can observe that
almost the whole time were consumed by the SMT-solver (the y axis has different scale
on both figures). Generating a quantifier-free first-order formula in every case took less
than 45 sec.</p>
        <p>Fig. 6 shows memory usage for the BMC algorithm and SMT-solver. We can
observe that for the formulae '1 and '3 the BMC algorithm did not use a lot of memory
and the SMT-solver consumed almost the whole memory in this case. For other
formulae the memory usage for BMC and SMT-solver is almost the same.</p>
        <p>Total time usage for the TGPP
5</p>
        <p>6</p>
        <p>Number of Nodes
2
3
4
7
8
9
10</p>
        <p>BMC memory usage for the TGPP</p>
        <p>SMT memory usage for the TGPP</p>
      </sec>
      <sec id="sec-5-4">
        <title>TTCS</title>
        <p>As we mentioned before, the number of considered k-paths (fk) for the translation
is always equal to 1. The length of the witness for the formula 1 is equal to 12 and for
the formula 2 is equal to 7. For the formula 3 the length of the witness is equal to 12
for two trains, 18 for three trains, 32 for four trains, and 38 for five trains.</p>
        <p>Total time usage for the TTCS
7000 ψψ21
6000 ψ3
5000
.ce 4000
s
n
i
iem3000
T
2000
1000
0
2 3 4 5 10 20 30 40 50 60 70 80 90 100 110 120 130 140 145</p>
        <p>
          Number of Trains
trains we have the opposite situation. The reason of this situation is the heuristic of the
SMT-solver. Z3 solver found the valuation faster. We think that the interesting future
work will be finding the optimal SMT file for SMT-solvers [
          <xref ref-type="bibr" rid="ref6">6</xref>
          ].
        </p>
        <p>Total memory usage for the TTCS</p>
        <p>1
1600 ψψ3</p>
        <p>2
1400
1200
B
inM1000
y
rom 800
e
M 600
400
200
0
2 3 4 5 10 20 30 40 50 60 70 80 90 100 110 120 130 140 145</p>
        <p>Number of Trains
0 2 3 4 5 10 20 30 40 50 60 70 80 90 100110120130140145</p>
        <p>Number of Trains
0 2 3 4 5 10 20 30 40 50 60 70 80 90 100110120130140145</p>
        <p>Number of Trains</p>
        <p>Fig. 9: SMT and BMC time usage for TTCS.</p>
        <p>BMC memory usage for the TTCS
0 2 3 4 5 10 20 30 40 50 60 70 80 90 100110120130140145</p>
        <p>Number of Trains</p>
        <p>SMT memory usage for the TTCS
We have implemented and experimentally evaluated an SMT-based BMC method for
real-time systems, which are modelled by timed automata with dense time, and for
properties expressible in MTL with the semantics over timed automata. We have
experimentally evaluated the method. The method is based on a translation of the existential
model checking for MTL to the existential model checking for LTLq, and then on the
translation of the existential model checking for LTLq to the satisfiability modulo
theories problem.</p>
        <p>In the future we would like to develop a corresponding SAT-based method.
Developing the SMT-based method as a first method was a natural way to solve the problem.
SMT encoding is easier to implement. However, the SAT encoding in many cases is
more precise, what may give better experimental results.</p>
      </sec>
    </sec>
  </body>
  <back>
    <ref-list>
      <ref id="ref1">
        <mixed-citation>
          1.
          <string-name>
            <given-names>R.</given-names>
            <surname>Alur</surname>
          </string-name>
          ,
          <string-name>
            <given-names>C.</given-names>
            <surname>Courcoubetis</surname>
          </string-name>
          , and
          <string-name>
            <given-names>D.</given-names>
            <surname>Dill</surname>
          </string-name>
          .
          <article-title>Model checking in dense real-time</article-title>
          .
          <source>Information and Computation</source>
          ,
          <volume>104</volume>
          (
          <issue>1</issue>
          ):
          <fpage>2</fpage>
          -
          <lpage>34</lpage>
          ,
          <year>1993</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref2">
        <mixed-citation>
          2.
          <string-name>
            <given-names>R.</given-names>
            <surname>Alur</surname>
          </string-name>
          and
          <string-name>
            <given-names>D.</given-names>
            <surname>Dill</surname>
          </string-name>
          .
          <article-title>A theory of Timed Automata</article-title>
          .
          <source>Theoretical Computer Science</source>
          ,
          <volume>126</volume>
          (
          <issue>2</issue>
          ):
          <fpage>183</fpage>
          -
          <lpage>235</lpage>
          ,
          <year>1994</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref3">
        <mixed-citation>
          3.
          <string-name>
            <given-names>Rajeev</given-names>
            <surname>Alur</surname>
          </string-name>
          , Tomás Feder, and
          <string-name>
            <surname>Thomas</surname>
            <given-names>A.</given-names>
          </string-name>
          <string-name>
            <surname>Henzinger</surname>
          </string-name>
          .
          <article-title>The benefits of relaxing punctuality</article-title>
          .
          <source>J. ACM</source>
          ,
          <volume>43</volume>
          (
          <issue>1</issue>
          ):
          <fpage>116</fpage>
          -
          <lpage>146</lpage>
          ,
          <year>1996</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref4">
        <mixed-citation>
          4.
          <string-name>
            <given-names>Rajeev</given-names>
            <surname>Alur</surname>
          </string-name>
          , Limor Fix, and
          <string-name>
            <surname>Thomas</surname>
            <given-names>A.</given-names>
          </string-name>
          <string-name>
            <surname>Henzinger</surname>
          </string-name>
          .
          <article-title>Event-clock automata: A determinizable class of timed automata</article-title>
          .
          <source>Theor. Comput. Sci.</source>
          ,
          <volume>211</volume>
          (
          <issue>1-2</issue>
          ):
          <fpage>253</fpage>
          -
          <lpage>273</lpage>
          ,
          <year>1999</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref5">
        <mixed-citation>
          5.
          <string-name>
            <given-names>Rajeev</given-names>
            <surname>Alur</surname>
          </string-name>
          and
          <string-name>
            <given-names>Thomas A.</given-names>
            <surname>Henzinger</surname>
          </string-name>
          .
          <article-title>Real-time logics: Complexity and expressiveness</article-title>
          .
          <source>In Proceedings of the Fifth Annual Symposium on Logic in Computer Science (LICS '90)</source>
          , Philadelphia, Pennsylvania, USA, June 4-7,
          <year>1990</year>
          , pages
          <fpage>390</fpage>
          -
          <lpage>401</lpage>
          ,
          <year>1990</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref6">
        <mixed-citation>
          6.
          <string-name>
            <given-names>Mislav</given-names>
            <surname>Balunovic</surname>
          </string-name>
          , Pavol Bielik, and
          <string-name>
            <surname>Martin</surname>
            <given-names>T.</given-names>
          </string-name>
          <string-name>
            <surname>Vechev</surname>
          </string-name>
          .
          <article-title>Learning to solve SMT formulas</article-title>
          .
          <source>In Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems</source>
          <year>2018</year>
          , NeurIPS
          <year>2018</year>
          ,
          <fpage>3</fpage>
          -8
          <source>December</source>
          <year>2018</year>
          , Montréal, Canada., pages
          <fpage>10338</fpage>
          -
          <lpage>10349</lpage>
          ,
          <year>2018</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref7">
        <mixed-citation>
          7.
          <string-name>
            <given-names>Stefano</given-names>
            <surname>Baratella</surname>
          </string-name>
          and
          <string-name>
            <given-names>Andrea</given-names>
            <surname>Masini</surname>
          </string-name>
          .
          <article-title>A two-dimensional metric temporal logic</article-title>
          .
          <source>CoRR</source>
          , abs/
          <year>1903</year>
          .05894,
          <year>2019</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref8">
        <mixed-citation>
          8.
          <string-name>
            <given-names>A.</given-names>
            <surname>Biere</surname>
          </string-name>
          ,
          <string-name>
            <given-names>A.</given-names>
            <surname>Cimatti</surname>
          </string-name>
          , E. Clarke, and
          <string-name>
            <given-names>Y.</given-names>
            <surname>Zhu</surname>
          </string-name>
          .
          <article-title>Symbolic model checking without BDDs</article-title>
          .
          <source>In Proc. of the 5th Int. Conf. on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'99)</source>
          , volume
          <volume>1579</volume>
          <source>of LNCS</source>
          , pages
          <fpage>193</fpage>
          -
          <lpage>207</lpage>
          . Springer-Verlag,
          <year>1999</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref9">
        <mixed-citation>
          9.
          <string-name>
            <given-names>Armin</given-names>
            <surname>Biere</surname>
          </string-name>
          , Alessandro Cimatti,
          <string-name>
            <surname>Edmund M. Clarke</surname>
            , Ofer Strichman, and
            <given-names>Yunshan</given-names>
          </string-name>
          <string-name>
            <surname>Zhu</surname>
          </string-name>
          .
          <article-title>Bounded model checking</article-title>
          .
          <source>Advances in Computers</source>
          ,
          <volume>58</volume>
          :
          <fpage>117</fpage>
          -
          <lpage>148</lpage>
          ,
          <year>2003</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref10">
        <mixed-citation>
          10.
          <string-name>
            <given-names>P.</given-names>
            <surname>Bouyer</surname>
          </string-name>
          .
          <article-title>Model-checking timed temporal logics</article-title>
          .
          <source>Electr. Notes Theor. Comput. Sci.</source>
          ,
          <volume>231</volume>
          :
          <fpage>323</fpage>
          -
          <lpage>341</lpage>
          ,
          <year>2009</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref11">
        <mixed-citation>
          11.
          <string-name>
            <surname>Patricia</surname>
            <given-names>Bouyer</given-names>
          </string-name>
          , Fabrice Chevalier, and
          <string-name>
            <given-names>Nicolas</given-names>
            <surname>Markey</surname>
          </string-name>
          .
          <article-title>On the expressiveness of TPTL and MTL</article-title>
          . Inf. Comput.,
          <volume>208</volume>
          (
          <issue>2</issue>
          ):
          <fpage>97</fpage>
          -
          <lpage>116</lpage>
          ,
          <year>2010</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref12">
        <mixed-citation>
          12.
          <string-name>
            <surname>Marius</surname>
            <given-names>Bozga</given-names>
          </string-name>
          , Jianmin Hou, Oded Maler, and
          <string-name>
            <given-names>Sergio</given-names>
            <surname>Yovine</surname>
          </string-name>
          .
          <article-title>Verification of asynchronous circuits using timed automata</article-title>
          .
          <source>Electr. Notes Theor. Comput. Sci.</source>
          ,
          <volume>65</volume>
          (
          <issue>6</issue>
          ):
          <fpage>47</fpage>
          -
          <lpage>59</lpage>
          ,
          <year>2002</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref13">
        <mixed-citation>
          13.
          <string-name>
            <given-names>Henning</given-names>
            <surname>Dierks</surname>
          </string-name>
          .
          <article-title>Plc-automata: a new class of implementable real-time automata</article-title>
          .
          <source>Theor. Comput. Sci.</source>
          ,
          <volume>253</volume>
          (
          <issue>1</issue>
          ):
          <fpage>61</fpage>
          -
          <lpage>93</lpage>
          ,
          <year>2001</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref14">
        <mixed-citation>
          14.
          <string-name>
            <surname>Deepak D'Souza</surname>
            and
            <given-names>Pavithra</given-names>
          </string-name>
          <string-name>
            <surname>Prabhakar</surname>
          </string-name>
          .
          <article-title>On the expressiveness of MTL in the pointwise and continuous semantics</article-title>
          .
          <source>STTT</source>
          ,
          <volume>9</volume>
          (
          <issue>1</issue>
          ):
          <fpage>1</fpage>
          -
          <lpage>4</lpage>
          ,
          <year>2007</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref15">
        <mixed-citation>
          15.
          <string-name>
            <surname>M. Kacprzak</surname>
            ,
            <given-names>W.</given-names>
          </string-name>
          <string-name>
            <surname>Nabialek</surname>
            ,
            <given-names>A.</given-names>
          </string-name>
          <string-name>
            <surname>Niewiadomski</surname>
            ,
            <given-names>W.</given-names>
          </string-name>
          <string-name>
            <surname>Penczek</surname>
            ,
            <given-names>A.</given-names>
          </string-name>
          <string-name>
            <surname>Pólrola</surname>
            ,
            <given-names>M.</given-names>
          </string-name>
          <string-name>
            <surname>Szreter</surname>
            ,
            <given-names>B.</given-names>
          </string-name>
          <article-title>Woz´na, and</article-title>
          <string-name>
            <given-names>A.</given-names>
            <surname>Zbrzezny</surname>
          </string-name>
          .
          <article-title>VerICS 2007 - a model checker for knowledge and real-time</article-title>
          .
          <source>Fundamenta Informaticae</source>
          ,
          <volume>85</volume>
          (
          <issue>1-4</issue>
          ):
          <fpage>313</fpage>
          -
          <lpage>328</lpage>
          ,
          <year>2008</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref16">
        <mixed-citation>
          16.
          <string-name>
            <given-names>Ron</given-names>
            <surname>Koymans</surname>
          </string-name>
          .
          <article-title>Specifying real-time properties with metric temporal logic</article-title>
          .
          <source>Real-Time Systems</source>
          ,
          <volume>2</volume>
          (
          <issue>4</issue>
          ):
          <fpage>255</fpage>
          -
          <lpage>299</lpage>
          ,
          <year>1990</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref17">
        <mixed-citation>
          17.
          <string-name>
            <given-names>W.</given-names>
            <surname>Penczek</surname>
          </string-name>
          ,
          <string-name>
            <surname>B.</surname>
          </string-name>
          <article-title>Woz´na, and</article-title>
          <string-name>
            <given-names>A.</given-names>
            <surname>Zbrzezny</surname>
          </string-name>
          .
          <article-title>Bounded model checking for the universal fragment of CTL</article-title>
          .
          <source>Fundamenta Informaticae</source>
          ,
          <volume>51</volume>
          (
          <issue>1-2</issue>
          ):
          <fpage>135</fpage>
          -
          <lpage>156</lpage>
          ,
          <year>2002</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref18">
        <mixed-citation>
          18.
          <string-name>
            <given-names>A.</given-names>
            <surname>Pnueli</surname>
          </string-name>
          .
          <article-title>The temporal logic of programs</article-title>
          .
          <source>In 18th Annual Symposium on Foundations of Computer Science</source>
          , Providence, Rhode Island, USA, 31 October - 1
          <source>November</source>
          <year>1977</year>
          , pages
          <fpage>46</fpage>
          -
          <lpage>57</lpage>
          ,
          <year>1977</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref19">
        <mixed-citation>
          19.
          <string-name>
            <surname>Vladislav</surname>
            <given-names>Ryzhikov</given-names>
          </string-name>
          , Przemyslaw Andrzej Walega, and
          <string-name>
            <given-names>Michael</given-names>
            <surname>Zakharyaschev</surname>
          </string-name>
          .
          <article-title>Data complexity and rewritability of ontology-mediated queries in metric temporal logic under the event-based semantics</article-title>
          .
          <source>In Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, IJCAI</source>
          <year>2019</year>
          , Macao, China,
          <source>August 10-16</source>
          ,
          <year>2019</year>
          , pages
          <fpage>1851</fpage>
          -
          <lpage>1857</lpage>
          ,
          <year>2019</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref20">
        <mixed-citation>
          20.
          <string-name>
            <surname>Mathijs</surname>
            <given-names>Schuts</given-names>
          </string-name>
          , Feng Zhu, Faranak Heidarian, and
          <string-name>
            <surname>Frits</surname>
            <given-names>W.</given-names>
          </string-name>
          <string-name>
            <surname>Vaandrager</surname>
          </string-name>
          .
          <article-title>Modelling clock synchronization in the chess gmac WSN protocol</article-title>
          .
          <source>In Proceedings First Workshop on Quantitative Formal Methods: Theory and Applications</source>
          ,
          <string-name>
            <surname>QFM</surname>
          </string-name>
          <year>2009</year>
          , Eindhoven,
          <source>The Netherlands, 3rd November</source>
          <year>2009</year>
          ., pages
          <fpage>41</fpage>
          -
          <lpage>54</lpage>
          ,
          <year>2009</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref21">
        <mixed-citation>
          21.
          <string-name>
            <given-names>Thomas</given-names>
            <surname>Wilke</surname>
          </string-name>
          .
          <article-title>Specifying timed state sequences in powerful decidable logics and timed automata. In Formal Techniques in Real-Time and</article-title>
          <string-name>
            <surname>Fault-Tolerant</surname>
            <given-names>Systems</given-names>
          </string-name>
          ,
          <source>Third International Symposium Organized Jointly with the Working Group Provably Correct Systems - ProCoS</source>
          , Lübeck, Germany, September 19-23, Proceedings, pages
          <fpage>694</fpage>
          -
          <lpage>715</lpage>
          ,
          <year>1994</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref22">
        <mixed-citation>
          22. B.
          <article-title>Woz´na-Szczes´niak and</article-title>
          <string-name>
            <given-names>A.</given-names>
            <surname>Zbrzezny</surname>
          </string-name>
          .
          <article-title>Checking MTL properties of discrete timed automata via bounded model checking</article-title>
          .
          <source>Fundam</source>
          . Inform.,
          <volume>135</volume>
          (
          <issue>4</issue>
          ):
          <fpage>553</fpage>
          -
          <lpage>568</lpage>
          ,
          <year>2014</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref23">
        <mixed-citation>
          23.
          <string-name>
            <surname>Boz</surname>
          </string-name>
          <article-title>˙ena Woz´na-Szczes´niak and Andrzej Zbrzezny. Checking MTL properties of discrete timed automata via bounded model checking</article-title>
          .
          <source>Fundam</source>
          . Inform.,
          <volume>135</volume>
          (
          <issue>4</issue>
          ):
          <fpage>553</fpage>
          -
          <lpage>568</lpage>
          ,
          <year>2014</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref24">
        <mixed-citation>
          24.
          <string-name>
            <given-names>Agnieszka</given-names>
            <surname>Zbrzezny</surname>
          </string-name>
          .
          <article-title>Selected SAT-</article-title>
          and
          <article-title>SMT-based model checking methods</article-title>
          .
          <source>PhD thesis</source>
          , Institue of Computer Science, Polish Academy of Sciences,
          <year>2017</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref25">
        <mixed-citation>
          25.
          <string-name>
            <given-names>Agnieszka</given-names>
            <surname>Zbrzezny</surname>
          </string-name>
          and
          <string-name>
            <given-names>Andrzej</given-names>
            <surname>Zbrzezny</surname>
          </string-name>
          .
          <article-title>Simple bounded MTL model checking for discrete timed automata (extended abstract)</article-title>
          .
          <source>In Proceedings of the 25th International Workshop on Concurrency, Specification and Programming</source>
          , Rostock, Germany,
          <source>September 28-30</source>
          ,
          <year>2016</year>
          ., pages
          <fpage>37</fpage>
          -
          <lpage>48</lpage>
          ,
          <year>2016</year>
          .
        </mixed-citation>
      </ref>
    </ref-list>
  </back>
</article>