In this paper, we propose a HDL IP generator for (Orthogonal Frequency-Division Multiplexing) OFDM modulators. This modulation is used in many telecommunication standards. However, each standard requires a specific OFDM modulator characterized by a diferent number of carriers and a cyclic prefix. These diferences, in terms of OFDM parameters, have a negative impact on RTL hardware design. This diversity makes dificult the reusing modulators already designed for a diferent project involving a diferent communication standard. For this reason, the authors propose an automatic IP HDL generator capable of generating RTL code in VHDL or Verilog of OFDM modulators with number of carriers and cyclic prefix settable by user. The generated IP have been characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX xc7z030 FPGA.
plementation. This design flow can be divided into two
steps: called front-end and back-end. The front-end
In the several last years, digital electronics have been phase consists of RTL design using HDL languages like
increasingly used in several fields. This is essentially VHDL, Verilog, or System Verilog. The back-end phase
due to the capability of modern integrated digital cir- involves the physical-design (the circuit layout).
cuits to provide high computational power allowing A hardware description language (HDL) is a
lanthe realization of complex (Digital Signal Processing) guage used to describe the architecture and behavior
DSP circuits [
The Hardware implementation of digital commu- Due to the exploding complexity of digital electronic nication systems both on ASIC and FPGA requires a circuits since the 1970s (see Moore’s law), synthesis very complex design flow. Such as a flow is extremely through HDL languages began a necessity. There are slow if compared with the one used for software im- two major hardware description languages: VHDL and Verilog.
SYSTEM 2020: Symposium for Young Scientists in Technology, The front-end phase is very slow because HDL lanE"ngrionbeeerrtian.gavaanndzMataot@hepmhdat.uicnsi,cOt.nitli(nGe., NMiacyot2r0a)2020 guages are very complex to develop and verify. In order to speed-up the RTL design phase, HDL Intellectual Property (IPs) are increasingly proposed in the lit© 2020 Copyright for this paper by its authors. Use permitted under Creative CPWrEooUrckReshdoinpgs IhStpN:/c1e6u1r3-w-0s.o7r3g CCoEmUmoRns WLiceonrsekAsthtriobuptioPnr4o.0cIneteerdnaitniognasl ((CCC EBYU4R.0)-.WS.org) erature and used by RTL engineers. IPs are re-usable blocks of HDL code that can either be taken from internal design libraries or be purchased from third-party vendors. Thanks to their re-usability and reconfigurability, IP cores allow the speed-up of the RTL design phase also for specific device design such as those in
In this paper, the authors propose an IP generation tool for OFDM modulators. The IP generator has been developed in MATLAB/SIMULINK. It allows users to select the number of carrier number, the length of the cyclic prefix. In addition, users can provide fixed-point information as the number of the bit of the inputs and of the outputs. The IP generator is capable to generate both VHDL and Verilog. The paper is organized as follows: In Sect.2 the OFDM modulation is described. In Sect.3 the IP generator and the OFDM Hardware architectures that are implemented are described. In Sect.4 the experimental results in terms of area speed and power consumption are provided. Finally in Sect.5 conclusions are provided.
Nowadays several communication applications require
high data-rate transmission over mobile or wireless
channels [
is the bit rate subcarriers, where each subcarrier has The principle of operation is based on the orthogonality of the subcarriers, whose concept is reported in isfying (1) are those reported in Figure 1(a). Thus, a generic OFDM signal can be written as: ( ) = ∑ ( ) 2
⋅ 2 0 where 0 is the Radio Frequency (RF) translation. When we sample the OFDM signal in (2) for = , we ob ( / ) = ∑ ( ) 2
which is the Inverse Fourier Transform ( transmitted symbols before the RF translation. In Fig
−1) of the ure 2 it is reported the classical scheme of the transmitter of an OFDM signal. In the demodulator at the receiver, we consider for example the frequency of subcarrier = / , the received signal is, after removing
modulator architecture and generate the VHDL or Verilog code the OFDM modulators. The IP is provided with 5 I/O ports divided into control and data ports. In the following, a detailed description of these port is provided giving information about the data size and the direction: • clock: it is a one-bit input port used to provide
the clock to the circuit. • reset: it is a one-bit input port used for the global
reset. The reset is asynchronous active high. • enable: it s a one-bit input port used for the
global enable. • ready: it is a one-bit input port. If the ready is low, the IP ignores the input. This port must be 1 when input data are available. • done: It s a one-bit output port. This port pass from zero to one when data are available at the output of the circuit • real-data: it s an N-bit Input port (N is selected
by the user) used to provide the real input sam• imag-data: it s an N-bit Input port (N is selected
by the user) used to provide the imaginary input • real-out: it s an N-bit output port (N is selected by the user) used to provide the real output samples ples samples 0
2 −
= ∑ ∫ 0 ( ) = ( ) (4) Due to the subcarrier orthogonality, the receiver is able to extract the correspondent complex symbol transmitted on th -th subcarrier.
In a wireless channel, multipath can afect the orthogonality due to delays and reflections can provide the receiver with replies. It is possible to have a guard time interval in order to properly start the reception, thus having the integration between Unfortunately, this is not enough since diferent termi+ . nals can transmitting simultaneously. In order to avoid an inter-carrier interference, a cyclic prefix is added to the transmitted signal as described in Figure 3.
The cyclic prefix allows to have an integer number of times the oscillation of the basic waveform 2 despite the reply comes late. Even if it partially leaves the integration interval thanks to the cyclic prefix, the missing part of the reply go back in the interval of interest without afecting the receiver. The only diference is that now the duration of the OFDM symbols are + , while the integration occurs for a time of seconds, thus reducing the collected energy of
√ Of course, the guard time should be selected properly, depending on the channel characteristics. should be greater than the maximum delay introduced by the wireless channel (at least greater than the channel delay spread) but as minimum as possible due to the loss + . in the energy collection.
In Figure 4 it is reported the generic scheme of the ( ) − 2 = ∑ ∫ ( ) 2 − 2 = The proposed IP generator has been developed in MAT
LAB. Using a graphical interface users can customize The QAM Mapper maps the I/Q inputs on a QAM constellation. In this first version of the core generator, only the 4QAM modulation is available. However future releases will include also other QAM modulation schemes. Fig.5 show the 4QAM constellation implemented in the proposed IP core.
The IFFT core is the complex element of the IP CORE in terms of hardware complexity. It is composed of Nlog2 Processing Element (PE) where N is the number of OFDM carriers and consequently the number of IFFT bins. Each processing element consists of a dualport RAM used for the ordering of the samples, a ROM containing the IFFT twiddle factors, a complex multiplier, and an address generator. The address generator and the dual-port RAM order the input using the double bufering technique.
A detailed description of this block is provided in Fig.7
In order to reduce the number of multipliers, the complex multiplication has been implemented using
In this Section, experimental results are provided. We use the proposed IP generator to generate the VHDL code of 9 OFDM modulators. These modulators difer from each other in terms of the number of carriers and cyclic prefix. In order to verify the correct behavior of the circuit, we performed several test benches using the RTL simulator models. Simulations are performed providing at the input of the IP sinusoidal waves and chirp. Simulation results are compared with theoretical results obtained by a MATLAB model especially realized for this purpose.
The generated VHDL files are has been synthesized using the XILINX Vivado toolchain. Synthesis and Place and Route have been performed with a clock constraint of 200 MHz. Implementation results have shown in Tab. 1 We varied the number of carriers from 8 to 2048 (considering only power of two). The second column of the table shows the cyclic prefix adopted for consumption correlated on the circuit area [30],[31].
There are three power dissipation components in CMOS digital circuits:
2. Short-Circuit Power 3. Static Power.
Among these contributions, the switching power represents the most important because one and it is deifned in Eq. 5 where a is the switching activity, C is the switching capacitance, f is the clock frequency and Vdd the supply voltage. = ⋅ ⋅ ⋅ 2 (5) The second contribution„ is related to the short-circuit currents flowing through the MOS transistors. It is strongly dependent on switching activity, clock freany test case. Results are in terms of LUTs, LUTRAM, quency, and supply voltage, but it also depends on the FF, BRAM, and DSP. In Fig.10 it is shown the dynamic design (for example the transistor ratios and the node power consumption required for the computation of waveforms). The third component, the static power, the test cases. Power consumption nowadays repre- depends on the leakage currents and it is related to the sents a crucial aspect of digital circuits design, espe- circuit design, the technology, and the supply voltage. cially for embedded systems. Such systems are usu- The first two power contributions are usually considally powered by batteries and for this reason, power ered together under the name of Dynamic Power. Beconsumption must be reduced as possible in order to cause our experiments are performed on FPGAs, we extend the battery life. For this reason, circuits must be did not consider the static power dissipation but also realized in order to minimize the area being the power the dynamic one. Static power consumption on FPGA
is always negligible if the FPGA is almost full. in terms of hardware resource usage. This is always true being the size of the FPGA selected considering the target In this paper, we presented an OFDM modulator IP project. generator suitable in all communication standards re
Finally Fig.9 show the Implemented circuit layout quiring a power of two FFT based OFDM. for the 2048 case. Results show that the hardware re- The proposed tool allows RTL designers to design sources required for the IP implementation are very lfexible OFDM modulators ofering the possibility to reduced, the power consumption increases with the customize the number of carriers, the cyclic prefix, and area following perfectly the theory. The choice to im- fixed-point. The IP has been characterized in terms plement complex product using only three multipliers of area, speed, and power consumption on a XILINX reduces the number of DSP involved in the implemen- xc7z030 FPGA. Results show a very eficient impletation. mentation requiring a reduced number of hardware resources. In the future, additional characterizations will be performed, in particular we will synthesize the VHDL code generated by the proposed IP Generator on ASIC. The synthesis will be performed using Synopsis. In addition, we will introduce other modulation schemes for the OFDM carriers. In order to further improve the performance of the future releases of the IP generator, we are considering the hypothesis to implement the IFFT architecture presented in [32]. This solution will allow reducing the hardware resources in particular the number of multipliers. This hardware simplification will introduce also a power consumption reduction.