RF Sampling of Wideband Signals Using Xilinx UltraScale+ RFSoC Francesco Di Francoa , Corrado Ramettab , Michele Russoa and Mario Vaccaroa a VICOSYSTEMS S.r.l V.le Odorico da Pordenone, 33, Catania, CT, Italy b Department of Computer, Control, and Management Engineering, Sapienza University of Rome, Via Ariosto 25, Roma, Italy Abstract New Xilinx RFSoC devices are very useful in modern telecommunication technology due to onboard RF data converters. Several technologies such as modern 5G or classical radar applications can benefit from that. Other advantages of using RFSoC with respect to traditional approaches are a high saving of power consumption and chip area. Since high-level development tools, such as Matlab/Simulink or High-Level Synthesis, fully support these devices, it is possible to easily implement high- bandwidth systems since modern and exploiting all RFSoC’s innovative capabilities. Keywords Xilinx UltraScale+ RFSoC, Time Interleaved ADC, Wideband Signals, FPGA, Parallel Computing. 1. Introduction Several applications are involved in new scenarios in- cluding satellite, rural and urban and smart city envi- ronments [1, 2, 3, 4]. Modern telecommunication technologies require an increasingly growing signal bandwidth. In this con- text, we can find several applications such as Digi- tal Beam Forming Networks (DBFN), Massive MIMO (MMIMO) and Carrier Aggregation (CA) Systems. An- other important example is given by newborn 5G tech- nology that exploits a large number of channels and Figure 1: Classic IF down-conversion and new RFSoC ap- high data-rates. Also radio-astronomy [5, 6] or Cog- proach with direct RF sampling nitive Radio [7] applications can benefit of this tech- nology. These signal features have required the devel- opment of new technologies by semiconductor firms The main concept behind new ADCs devices is Time with the aim to optimize the single-chip power con- Interleaving (TI) sampling. sumption mostly focusing their effort on Radio Fre- quency Digital Front End (DFE/RF) [8, 9]. For instance, in the last years, Xilinx firm has placed 2. Time Interleaving ADCs on the market several Systems-on-Chip (SoC) equipped with new components that try to make up for the per- The TI is a technique that allows to sample high fre- formance deficiencies of the systems already on the quency signals by using more low sample-time ADC 𝑓𝑠 market. In details, the new UltraScale+ RFSoCs by Xil- cores at the same time. Each ADC core works at 𝑀 inx [10] are equipped with new high-speed and high- where 𝑀 is the number of ADC cores and 𝑓𝑠 is the bandwidth ADC/DAC that allow to sample and recon- equivalent sample frequency of whole system. For in- struct analog signals directly at RF [11] avoiding any IF stance, if 𝑓𝑠 = 1𝐺𝐻 𝑧 and 𝑀 = 4, each ADC core will down-conversion middle step as depicted in Figure 1. work at a frequency of 250 MHz and the input signal will be sampled in different instants by each core as ICYRIME 2020: International Conference for Young Researchers in shown in Figure 2. Informatics, Mathematics, and Engineering, Online, July 09 2020 " f.difranco@vicosystems.it (F.D. Franco); The clear advantage of this approach is the possi- m.russo@vicosystems.it (M. Russo); m.vaccaro@vicosystems.it (M. bility to digitalize an analog signal by using a clock Vaccaro) frequency lower than the Nyquist frequency. On the  Β© 2020 Copyright for this paper by its authors. Use permitted under Creative other hand, TI-ADC digital output is very sensitive CEUR Workshop http://ceur-ws.org ISSN 1613-0073 Commons License Attribution 4.0 International (CC BY 4.0). CEUR Workshop Proceedings (CEUR-WS.org) to the so-called Interleaving Spurs (IS) [12] caused by Proceedings Figure 2: Operating principle of a TI-ADC Figure 5: RF Data Converter Evaluation Tool Figure 3: TX and RX JESD204 interfaces present a Soft-Decision Forward Error Correction (SD- FEC). The integration of these components in the same die allows to save area but mostly power (about 50%). Also the design of the board is simpler since the RF sig- nal is directly sampled without further down-conversi- ons. The classic approach for communicate with fast external converters exploits the JESD204 interface [14] as depicted in Figure 2 , but by integrating the convert- ers inside the SoC, it is possible to avoid this interface with a consequent further power saving. With current technology, RFSoC devices allow to di- rectly sample RF signals until 6 GHz. For this reason, they are very suitable for applications using bands L, S and C: Figure 4: RFSoC block diagram β€’ Multi-band networks such as 5G β€’ Massive MIMO channels mismatch. The same operating principle is likewise applied to Digital to Analog Conversion (DAC) β€’ Phased Array Radar that can be adopted in [13]. β€’ Satellite communications 3. RFSoC overview β€’ Measurements instrumentation The general block diagram of RFSoC is shown in Xilinx Zynq Ultrascale+ RFSoC is the first example of Figure 2. multi GS/s converters, programmable logic and ARM The RFSoC data conversion subsystem is composed cortex system integration in the same SoC. It is also of several RF Analog-to-digital and Digital-to-analog 17 Figure 6: Adjacent channel interference measurement converters, with the possibility to manage real and com- 3.3. RF Data Converters plex signals (I/Q). The structure of ADCs is based on Both ADC and DAC converters, use low-noise phase tiles. Each tile is composed of 4 ADCs and 1 PLL with PLLs for direct clock synthesis. As introduced above, 12 or 14 bits operation mode. In the same way the tiles ADC tiles are organized in tiles containing two (4 GSps) of DAC are organized with 4 14 bits DACs and 1 PLL or four converters (2 GSps), one PLL and some ded- with a bandwidth of 4 GHz and output frequency until icated DSP blocks. In the tile with 4 converters, the 5 GHz. The device is 40x40-mm in size, with a 1517- converters are organized in pairs, and each pair can be pin ball grid array (BGA) package and is manufactured configured separately. Figure 3.1 depicts the internal with a 16-nm Fin field-effect transistor (FinFET) pro- structure of ADC and DAC tile respectively. cess [15]. The NSD value for DACs is usually about -160 dBm/Hz with an output carrier of 3.5 GHz. For ADCs, the value 3.1. Processing System and of NSD is about -153 dBm/Hz with a single input tone Programmable logic at 3.5 GHz. The most complex allows the use of 8 chan- nels both for transmission and reception for a total of Like other Xilinx Zynq-based family, also RFSoC de- 16 converters with a power consumption of 9 Watt. vices contain on the same chip both a processing sys- tem (PS) and programmable logic (PL). The processing system is composed of a 64-bit ARM Cortex A53 pro- 3.4. How to use RFSoC converters cessor (1.3 GHz) used for applications and ARM Cor- RFSoC fully support AXI-Stream interface, that allow tex R5 (533 MHz) for real-time purposes. 4 channels of an high bandwidth. Furthermore, thanks to RF Data PS-GTR transceivers pairs that support data rates up Converter tool, the user can avoid to write complex to 6Gb/s are also present. hdl controls, since a large part of the settings can be The programmable logic uses CLBs with eight 6- set from this GUI. Figure 3.1 shows the flow to manage input LUTs and 16 FFs and it is equipped with 28 Gb/s RFSoC parameters and configuration. tranceivers. Xilinx also provides an IP core (Zynq Ultrascale+ Zynq Data Converter) for Vivado tool. The IP core can 3.2. Parameters Setting be used for both RF-ADC and RF-DAC configuration as shown in Figure 3.4. Xilinx provides a graphical RF Data Converter Evalu- Also other tool companies now supports these new ation Tool that easily allows to set all data converter devices. One of the most important is Mathworks, that parameters. The GUI is shown in Figure 2 and it al- allow to generate HDL code of complex DSP systems lows to measure some quantities such as Noise Spec- including AXI-stream interface for RFSoC device (see tral Density (NSD), third-order Intermodulation Dis- Figure 3.4. tortion (IM3), Adjacent Channel Leakage Ratio (ACLR). The latter is measured by creating a loopback between ADC and DAC as shown in Figure 3.1. 18 Figure 7: The Adjacent channel interference measurement Figure 8: Platform development flow Figure 10: Matlab/Simulink HDL support for Xilinx RFSoC 4. Conclusion In this paper, we presented the main features and po- tential of Xilinx RFSoCs. Thanks to RF converters (un- til 6 Gsps) they are very suitable for direct sampling of RF signals with bandwidth up to 4 GHz. As well as Figure 9: Vivado IP core for RFSoC being fully supported from Vivado tool, these devices are also supported by other tools such us Mathworks Simulink. 19 References [11] Xilinx, An Adaptable Direct RF-Sampling Solu- tion, Technical Report, 2019. [1] L. Cicala, C. Angelino, N. Fiscante, S. Ullo, [12] G. Manganaro, D. Robertson, Interleaving adcs: Landsat-8 and sentinel-2 for fire monitoring at a Unraveling the mysteries, Analog Dialogue 49 local scale: A case study on vesuvius, in: 2018 (2015). IEEE International Conference on Environmen- [13] R. Giuliano, F. Mazzenga, A. Vizzarri, Satellite- tal Engineering (EE), IEEE, 2018, pp. 1–6. based capillary 5g-mmtc networks for environ- [2] G. Borowik, M. Wozniak, A. Fornaia, R. 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