In IT world to design long life battery device designers need to improve features with low power consumption and low latency. IoT is widely expanding network of multi sensors and devices system which created the network with surrounded environment. Some of these systems are based on batteries for operate, so a new technology is required to design long life batteries without affecting performance of devices. This paper dealt with Low power management for IoT devices for extending their life and discussed about power sources of IoT system designs and techniques to minimize the power. Also focused on Clock Gating Technology implementation to IoT system network because it is widely used for power reduction in VLSI/ULSI chip designing. Low power IoT devices have many more applications in different fields like as Smart home, Smart Warehouse, Health wear application, Hospitality, Transportations and Industrial Application.
In today’s scenario IoT systems used widely in different applications like as medical, hospitality systems, smart home systems, transportations systems, energy systems, digital machine systems, smart grid style etc. IoT can be defined by connecting things of everyday life to robotics world with electronics, software and sensors. Simply, IoT can be described as term ‘Smart’, with connecting internet it send the information, receive the information and both. Because of this ability to send/receive information or both, it called Smart Technology to connecting internet to world. For collecting and sending the information IoT used the various types of sensors which automatically collect the information from the surrounding environment and allow to take actions in a right way. IoT platform is known as a biggest network to connecting or communicating various physical objects that contains embedded technology with their internal states and external environments.IoT basically expanding the interdependence of humans to interact contribute and collaborate to each thing which surrounded environment. This is much more safe, secure, effortless and time saving environment which exists. Saving time is more powerful feature to design IoT. Also IoT has benefit for efficient Resource Utilization, minimize Human Effort and save time, improve security. A huge collection of data needed to designing an IoT system which processing, computing and controlling over different internet servers/layers. Data which collected and evaluated in IoT systems includes audio or video form from different sources, this data known as big data, analyzed and controlled by number of sensors/actuators. Various issues associated with emerging Big Data like as storage power demand for processing, high latency, etc.
IoT devices are playing important role in daily life of human being like as mobile phone. With using IoT devices time saving is more. VLSI and Low power VLSI has many more challenges and opportunities with IoT design. An IoT system design requires low power and low price on small chips. IoT designers still are working on power management solution for low power design. The need of low power consumption in system design is very necessary as market requirements. IoT designers need to be design low power sensors, memories which used them to develop IoT system design with more power saving. Designers required novel low power scheme for the combination of low power operation, sensing, computation, and communication. IoT system designers required designing low power and energy consumed network system with low latency and cost as per market requirement, reliability and availability of system in every field. IoT systems are connected with different embedded systems which need to less power consumption or large saving of energy. The modern IoT system network required a wide range of power management, so designers need to be design low power and energy saving devices with identified power sources based on a specific application. Power/energy dissipation is a most common issue for designing high-performance systems. Many more low power technologies in IC world are invented by different designers and researchers. Some of widely used techniques in low power field are described in next section.
It is better to consider power in all stages of the system such as software and hardware design, system board design or a chip design. There are several stages for low power integrated circuit (IC) design. Many low-power design techniques introduced which can be used to design LP-IC. Some of effected low power techniques are discussed as below which are proved better solutions for power management in IC design world. 1) Power Gating Technique– This is the more power saving scheme because of leakage power reduction. During shutdown and sleep/active nodes the more power saving achieve in this technology. A simple structure for PG technique is shown in Figure 1 as below. Where two sleep transistors are shown as header and footer switches of network. These switches added to reducing leakage power in logic blocks when circuit is not in used. This technique is implemented for a device which has a large sleep time and work in the inactive mode during the operation of device. Therefore energy is saved as less power consumption during the sleep time 2) Power Matching Technique– This technology is based on selection of battery according to cells capacity for operating the device. The power matching scheme achieved good stability and wide bandwidth simultaneously. In this scheme the power is managed by transceiver nodes and internal nodes to allow the continuity in power flow at low currents. 3) SPCPM Technique- This technique used for power control in different components of IoT system designing. SPCPM is stand for Simultaneous power control and power management (SPCPM), this technology is based on sleeping node technique as simultaneous. Power/Energy transmitted in number of packets which maximized with sleepy/active nodes and kept the energy in terms of time varying amount. Transmitted Power or Energy optimized through monitoring a time based pattern. 4) Predictive Energy Allocation Technique- In this technique energy allocation can be done in terms of parameters impacting. It is used to provide to speculate the future energy generation rate. Also it helps to power tracing for evaluating the rate of energy utilization, power failure time and power loss in system. Simple diagram of energy allocation technique is shown in figure 2 as below. There is workload is consider as input which include a big data information for different applications. Scheduler used to schedule the data with different tasks to corresponded application server. The waiting queue generated for data transmissions over different network and applications. Generally this energy-efficient allocation technique implemented for distributing the resources in a heterogeneous data center. 5) Power Capping-Power Capping technology is restricted the power consumption in IoT design network to a safe level. Generally power consumption is achieved as a design time estimation which called thermal design power (TDP). Limitation of this technique is that the thermal violations may occur to the system. This scheme used a feedback system for manage the power from designing to runtime process through a Dynamic Voltage Frequency Scaling (DVFS). DVFS used as a computing and scheduling factor for the power management.
In IC design a large number of clock pulses used for design high frequency systems. These, extra clock pulses form a part of power dissipation which affected the circuit performance. Thus, the clock gating technique used to reduce power from extra clock activities. The Clock Gating technique achieved low power consumption with reducing unwanted clock switching activities during the circuit is not working. A simple explanation of clock gated technology is shown in figure 3 as below. In latch based CG technique, a level sensitive D-latch is used to hold the enabled signal. The enabled signal generated from the active edge of the clock and it is hold until the generation of complete clock pulse. Clock Gating technology implementation in IoT system design with different components is shown with following diagram as below. Design of low power components like as low power FSM, RAM, Register, Processor, Controller, Sensor is necessary in IoT system network. Clock gating reduced a significant amount of dynamic power. Also the area reduction achieved with CG scheme by using the multiplexers logic at inputs of the flip-flops. This technique uses negative edge latch and used AND gate to implement low power system design. Gating technology easy to implement the design with effected solution. Low power register design implementation shown in figure 4 and 5, where AND gate based CG implementation used for gating the clock signal and get the reduction in power.
VLSI IoT systems have more applications in AI area, agriculture area and smart digital systems era but more power consumed by the components which used to design complete systems, so power saving is common issue for each application. This paper specified the requirement of power management for IoT system design. IoT designers need to be design Low power consumed devices to designing system with high speed and faster. IoT designers have challenge to find more power management in integrated circuit. These designs can be used in a wide range of applications as the automotive, consumer, and industrial markets and grow up the technology with their new concepts in the field of low power IoT devices.
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