=Paper=
{{Paper
|id=Vol-3058/paper21
|storemode=property
|title=Methods For Integration Of III-V Compound And Silicon Multijunction Solar Cell
|pdfUrl=https://ceur-ws.org/Vol-3058/Paper-040.pdf
|volume=Vol-3058
|authors=Divya Sharma,Rajesh Mehra,Balwinder Raj
}}
==Methods For Integration Of III-V Compound And Silicon Multijunction Solar Cell==
https://ceur-ws.org/Vol-3058/Paper-040.pdf
Methods for Integration of III-V Compound and Silicon
Multijunction Solar Cell
Divya Sharma1, Rajesh Mehra2 and Balwinder Raj3
1,2,3
Panjab University, NITTTR Chandigarh, India
Abstract
Developing high-performance & economical solar cells are one of the fundamental aims to
achieve an economical levelised price of energy. On comparison, it can be easily visualized
that silicon based solar cells have just about to reach on the verge of efficiency threshold i.e
nearly 25%. On the other side, III-V solar cells are gradually exhibiting performance
advancement with an increment of almost 1% per year, with current recorded PCE of nearly
45%. Assimilation of these III-V solar cells on comparatively economical Silicon layer has
stimulated massive curiosity towards forthcoming energy plans by coalescing the advantages
of III-V constituents with inexpensive & largely available Silicon. This paper will elaborate
recent evolvement of III-V cell deposition over Silicon layer. Further, fundamental design
principles & the technical contentions w.r.t coalition of III-V solar cells on Silicon layer are
elaborated. Various methods for coalescing III-V solar cells over Si layer through
heteroepitaxial coalition & by mechanical stacking technique are discussed. With reduction
in cost of silicon solar cells, complemented with huge space existing for enhancing the III-V
solar cell PCE, the forthcoming visions for efficacious coalition of III-V solar cell over
Silicon layer seems highly favorable to begin an epoch of forthcoming generation of high
PCE & economical solar cells.
Keywords 1
Multijunction, High Efficiency, III-V-on-Si solar cells, hetero-epitaxial integration,
mechanical stacking.
1. Introduction
Today, III-V multijunction solar cells are used as effective technology in space power applications
[1]. Although, these cells have exhibited the highest energy conversion efficiency among all the
available solar cells, yet their expensiveness has been the principal barrier in their extensive use in
terrestrial applications. As already discussed, single junction/monojunction (1J) Silicon solar cells
have exhibited PCE of 25.6% which consists of 0.6% improvement in efficiency during the last 15
years [2]. Systematic design of Single Cell is illustrated in Fig.1. However, III-V solar cells have
gradually exhibited improvement at the rate of 1% efficiency increase per year, with record 44.7 %
efficiency at 297 suns by a 4J III-V solar cell [3]. Further, the supremacy of silicon cells in market
with reducing cost in current scenario has challenged the III-V solar cells to create a robust
commercialization effect. Expensiveness of starting substrate i.e. GaAs and Ge results in expensive
III-V solar cells. Effective combination of III-V solar cells over Silicon layer offers a huge potential
for reducing the future levelized energy price by combining advantages of group III-V constituents
with inexpensive & largely available Silicon substrate. Silicon not only possess significantly low price
corresponding to the larger area & cheaper Silicon substrate, but also have the properties like better
mechanical strength & higher thermal conductivity compared to Ge & GaAs substrates. III-V solar
cell coalition over Silicon layer may possibly utilize Silicon layer as an active lowermost sub cell.
International Conference on Emerging Technologies: AI, IoT, and CPS for Science & Technology Applications, September 06–07, 2021,
NITTTR Chandigarh, India
EMAIL: divya13jan@gmail.com (A. 1); rajeshmehra@nitttrchd.ac.in (A. 2); balwinderraj@gmail.com (A. 3)
ORCID: 0000-0002-3787-5017 (A. 1); 0000-0002-8014-4922(A. 2); 0000-0002-3065-6313(A. 3)
©2021 Copyright for this paper by its authors.
Use permitted under Creative Commons License Attribution 4.0 International (CC BY 4.0).
CEUR Workshop Proceedings (CEUR-WS.org)
Possessing a bandgap of 1.12 eV, Silicon layer may be considered as a better lowermost cell
contender compared to Germanium layer possessing 0.67 eV bandgap, for coalition with 2J
InGaP/GaAs solar cell. The subsequent trio-junction InGaP/GaAs/Si formed are swiftest path for III-
V-on-Si solar cells [4] carrying hypothetical efficiency more than 40% in AM1.5g & AM1.5d [5].
Current research has unveiled that shifting from a four inch Ge substrate to an eight-inch Si substrate
will result in 60% decline in price for multijunction solar cells [6].
Figure 1: Schematic design of Single solar cell
The exploration w.r.t coalescing III-V over Silicon layer for PV use was started during 80s.
Nevertheless, the intricacy linked with the constancy, material growth & manufacturability result in
declination in further exploration of III-V over Silicon solar cells during late 90s. During the past 5-6
years, III-V over Silicon solar cell, exploration for the same has again conferred attention w.r.t work
on recent buffer technique & mechanical stacking methods. Including reduced price of Silicon, in
association with remarkable scope existing for enhancing efficiency of III-V solar cells, forthcoming
prospects for efficacious coalition of III-V over Silicon layer seems highly encouraging. This paper
elaborates technical challenges and design criteria linked with coalescing III-V solar cells over Silicon
layer. Further, various processes for coalescing III-V solar cells over Silicon layer through
heteroepitaxial coalition & through mechanical mounding is elaborated. Finally, opportunities and
future prospects towards further advancement of the efficiency of III-V solar cell over Silicon layer
are presented.
2. Design criteria
Fundamental methodologies for coalescing III-V-on-Si substrate solar cellsare: heteroepitaxial
growth (or monolithic) & mechanical stacking (wafer bonding). The subsequent segments analysis the
fundamental design phenomenon & technical hitches linked to the abovementioned coalition
techniques.
2.1. Heteroepitaxial integration technique
Heteroepitaxial integration approach is alleged as very encouraging way to assimilate III-V solar
cells over Silicon layer utilizing mono substrate & single epitaxial method [9]. Lattice- matched
InGaP/GaAs solar cells are the basic ingredient in 3J and 4J III-V solar cells. Figure 2 illustrated the
schematic design of the trio- junctionGaInP/GaAs/Si solar cell [5]. Therefore, it can be easily
assumed that coalition of GaAs over Silicon layer was the preliminary & normal option for
establishing a strong stage for the forthcoming multijunction solar cell development [10]. Current
methodologies that include metamorphic graded buffers vizGaAsP and SiGe are receiving a huge
attention for III-V over Silicon solar cells [11]. Other heteroepitaxial coalition techniques, which are
yet to be extensively explored are as follows-(i) lattice-matched dilute nitride solar cells over Silicon
layer [12], (ii) lattice-mismatched InGaN solar cells over Silicon layer [13, 14].
Figure 2: Schematic design of the trio junction GaInP/GaAs/Si solar cell
Most discerning obstacles linked to heteroepitaxial coalition of III-V materials over Silicon layer are
as follows:
2.1.1. Growth of lattice-mismatched III-V-on-Si substrate materials
Lattice-mismatch of 4% among Si & GaAs &materials force the direct lattice growth of GaAs over
Silicon layer awfully difficult, causing in creation of threading & misfit dislocations which have a
pernicious effect on the carrier lifespan & subsequently on PCE. The popular methods employed for
GaAs lattice growth over Silicon layer to decrease the defect & dislocation density incorporate
annealing, [15] the low growth rate technique and low temperature throughout the preliminary GaAs
nucleation over Silicon layer [13]. Developing denser GaAs buffers results in dislocation declination
[13] however this results in cost inflation & increase the time of the epitaxial method. Figure 3
illustrated the mechanisms of dislocation motion in III-V surface heteroepitaxially grown on Silicon
layer [16]. Furthermore, thin strained films and superlattices added to the dense GaAs buffer results in
the eradication of TDs & reduce dislocation distribution in active films. These methods result in
maximum PCE w.r.t heteroepitaxial monojunction GaAs over Silicon solar cells [16]. Current
methods comprise of the development of metamorphic graded buffers to link the lattice constant
among Silicon & GaAs/ GaAsP layers [11]. In this regard use of graded SiGe buffers leads to
reduction in dislocation, however, these buffers are dense. In addition, these have lower bandgap
which prevents the use of silicon substrate to be used as bottommost cell. GaAsP buffers have larger
bandgap which may evade the condition of using Silicon substrate as an active sub cell.
Figure 3: Mechanisms of dislocation motion in III-V film heteroepitaxially grown on Si substrate
2.1.2. Heteroepitaxy of polar III-V materialson Ge/Si substrate
Development of multiatomic, heterogenous semiconductors(SC) over monoatomic semiconductors
consequences in emergence of structural defects viz antiphase domains, produced because of
heteroepitaxy of GaAs (polar materials) over Ge/Si (non-polar materials). The plane of Silicon film
[001] comprises of monoatomic phase where these atoms of Silicon are organized as dimers aligned
perpendicularly through adjacent phases. During the development of GaAs over Silicon layer, the
arsenic dimers align themselves perpendicularly across the nearby steps resulting in the generation of
Ga-Ga or As-As bonds,which induces the development of antiphase boundaries.
2.1.3. Thermal mismatch between III-V materials & Silicon substrate
Thermal expansion coefficient difference (2.6 × 10−6 °C−1 for Siand 5.73 × 10−6 °C−1 for GaAs) &
lattice-mismatch variation between GaAs and Silicon layer, result in residual strain in the layer of
defects & dislocations which leads to imperfect crystalline quality. Thermal mismatch results in
formation of microcracks in the GaAs epitaxial layer causing severe problems pertaining to solar cell
reliability in addition to restricting the cell area and efficiency. It is important to mention that faster
cooling rate stimulates microcrack generation, therefore it is imperative to regulate the rate of cooling
to curtail the microcrack generation.
2.1.4. Buffer design-electrical conductivity, optical transparency, thickness, &
surface passivation.
Appropriate buffer assortment is very important for successful performance of III-V over Silicon
solar cells. Transpicuous & thin buffer layers are required to exploit initial Silicon layer as active cell.
Further, the conductivity of the buffer is essential for concentrated PV cell to reduce resistance.
Metamorphic arranged buffer technique employs a dense buffer layer to link the lattice constant
among III-V materials & Silicon layers. Wide bandgap GaAsP type buffer is superior option
compared to low bandgapSiGe buffers for appropriate transparency for active bottom silicon cell [11].
2.2. Mechanical stacking/ mounding approach for III-V over Silicon
integration
Mechanical stacking w.r.t III-V over Silicon coalition may withstand large volume of lattice
mismatch & allows the coalition of materials with appropriate arrangement of bandgap that are devoid
of lattice- mismatch constrictions. The vital challenges linked with the mechanical mounding
technique for assimilating III-V materials over Silicon are as follows:
1. The temperature of bond should be attuned to the group III-V materials &Silicon substrate.
2. The bonding film should be transpicuous& thin to utilize bottom Silicon substrate as active
subcell.
3. For functioning of bi-junction solar cell in concentrated light, it is very important to
comprehend the conductive bond films to evade series resistance.
4. Bonding edges must possess minimal surface roughness & should devoid of oxides.
5. Feasible removal of III-V layer & reutilization method with higher yield.
3. Design of III-V & Si solar cell
Silicon usually restricts total current once unified in tandem with bi-junction InGaP/GaAs PV cells
in trio-junction arrangement [5, 17]. Therefore, the configuration of lower Silicon subcell is very
essential for current-synchronizing in tandem cell configuration. Other role of the III-V over Silicon
layer is to function as efficacious optical film, permitting adequate light diffusion, surface passivation,
sufficient carrier transfers and, minimizing carrier rebound. Generation of Emitter in the Silicon layer
is difficult & various techniques are reconnoitered, viz in-situ epitaxial phosphorus diffusion [18], in-
situ epitaxial growth of Silicon emitter [19] & ex-situ traditional diffusion. The in-situ phosphorus
diffusion is found less intensive for ideal junction formation in Silicon [19, 20]. The upper III-V cell
captivate the maximum photons of the optimum wavelength & only high energy photons will
diffuseto nethermost Silicon cell, therefore providing lesser impact on Jsc of silicon solar cell. Silicon
emitters of smaller dimensions are desired to make best use of both Voc&Jsc keeping boundary
recombination velocity small. Nevertheless, there persists a solid deadlock between improving
Voc&Jsc keeping interface recombination velocity high [21, 22]. The most essential design technique
for exploiting Silicon as an active cell with III-V cells, in a multijunction design is to contrive the rear
side of the Silicon layerto improve the rear surface rebound and attain good surface passivation since
Silicon subcell usually restricts the current in III-V/Si tandem cell configurations [5, 17].
4. Conclusion
In short, III-V over Silicon multijunction PV cells are recuperating attention because of their
ability to look after the forthcoming levelised price of energy and to amalgamate the improved PCE
benefits pertaining to III-V compounds with inexpensiveness & adequacy of Silicon. Various methods
for coalescing III-V on Silicon substrate are summarized. Essential design configuration, various
challenges & different methods are studied to minimize the dislocation density by using thin &
transpicuous buffers to comprehend Silicon as active bottom PV cell. Effective use of the nethermost
Silicon layer as active cell needs rear side Silicon layer engineering to elevate current density of
Silicon cell. Circumspect thought of design challenges will be essential w.r.t the realization of
forthcoming improved efficiency & cheaper III-V over Silicon layer multijunction solar cells. Various
heteroepitaxial & mechanically stacked integration techniques have paved the way to numerous
opportunities for new III-V on Silicon layer multijunction PV cell. Current researches in the
heteroepitaxial and the mechanically stacked integration technique have made it possible to think
about the efficiency more than exceeding 40% under concentrated sunlight, signifying an encouraging
future for III-V over Silicon PV cell technologies.
5. References
[1] I. Garcia, I.R. Stolle, I. Lombardero, L. Cifuentes, H. Nguyen and A. Morgan, “Space III-V
Multijunction Solar Cells on Ge/Si virtual substrates”, IEEE European Space Power
Conference (ESPC), pp.1-6, 2019.
[2] M.A. Green, K. Emery, Y. Hishikawa, W. Warta, and E.D. Dunlop, “Solar Cell Efficiency
Tables (Version 44)”, Progress in Photovoltaics: Research and Applications, vol. 22, pp.701–
10, 2014.
[3] A.W. Bett, S. P. Philipps, S. Essig, S. Heckelmann, R. Kellenbenz, V. Klinger, M. Niemeyer,
D. Lackner, and F. Dimroth, “Overview about Technology Perspectives for High Efficiency
Solar Cells for Space and Terrestrial Applications”, In Proc. 28th European Union-Photovoltaic
Solar Energy Conf., pp. 1-6, 2013.
[4] M.A. Green, “Silicon Wafer-based Tandem Cells: The Ultimate Photovoltaic Solution?”, In
Proc. Spie, Physics, Simulation, and Photonic Engineering of Photovoltaic Devices III, vol.
8981, pp. 89810L-1- 89810L-6, 2014.
[5] K. Derendorf, S. Essig, E. Oliva, V. Klinger, T. Roesener, S. P. Philipps, J. Benick, M. Hermle,
M. Schachtner, G. Siefer, W. Jager and F. Dimroth, “Fabrication of GaInP/GaAs//Si Solar Cells
by Surface Activated Direct Wafer Bonding”, IEEE Journal of Photovoltaics, vol. 3, no. 4,
pp.1423-1428, 2013.
[6] S. D’Souza, J. Haysom, H. Anis, and K. Hinzer, “The down-to- earth future of Si substrate
multi-junction concentrator photo- voltaics”, IEEE Electrical Power and Energy Conf., pp.57-
61, 2011.
[7] D. Shahrjerdi, S. W. Bedell, C. Ebert, C. Bayram, B. Hekmatshoar, K. Fogel, P. Lauro, M.
Gaynes, T. Gokmen, J.A. Ott and D.K. Sadana, “High-Efficiency Thin-Film InGaP/InGaAs/Ge
Tandem Solar Cells Enabled by Controlled Spalling Technology”, Applied Physics Letters, vol.
100, pp.053901-3, 2012.
[8] R. Tatavarti, A. Wibowo, G. Martin, F. Tuminello, C. Youtsey, G. Hillier and N. Pan,
“InGaP/GaAs/InGaAs Inverted Metamorphic (IMM) Solar Cells on 4” Epitaxial Lifted off
(ELO) Wafers”, In Proc. 35th IEEE Photovoltaic Spec. Conf., pp. 002125-002128, 2010.
[9] M. Feifel, D. Lackner, J. Ohlmann, K. Volz, T. Hannappel, J. Benick, M. Hermle, and F.
Dimroth, “Advances in Epitaxial GaInP/GaAs/Si Triple Junction Solar Cells”, 47th IEEE
Photovoltaic Specialists Conference (PVSC), 2020.
[10] T. Soga, T. Kato, M. Yang, M. Umeno, and T. Jimbo, “High Efficiency AlGaAs/Si Monolithic
Tandem Solar Cell Grown by Metalorganic Chemical Vapor Deposition”, Journal of Applied
Physics, vol. 78, pp. 4196-4199, 1995.
[11] M. Diaz, L. Wang, A. Gerger, A. Lochtefeld, C. Ebert, R. Opila, I.P. Wurfl and A. Barnett,
“Dual-Junction GaAsP/SiGe on Silicon Tandem Solar Cells”, In Proc. 40th IEEE Photovoltaic
Spec. Conf., pp. 0827-0830, 2014.
[12] K. Yamane, N. Urakami, H. Sekiguchi, and A. Wakahara, “III-V- N Compounds for Multi-
Junction Solar Cells on Si”, In Proc. 40th IEEE Photovoltaic Spec. Conf., pp. 2792-2796, 2014.
[13] B.T. Tran, E.Y. Chang, H.D. Trinh, C.T. Lee, K.C. Sahoo, K.L. Lin, M.C. Huang, H.W. Yu,
T.T. Luong, C.C. Chung and C.L. Nguyen, “Fabrication and Characterization of n-
In0.4ga0.6n/p-Si Solar Cell”, Solar Energy Materials & Solar Cells, vol. 102, pp. 208-211,
2012.
[14] D. Benmoussa, H. Khachab and H. Benslimane, “Simulation of the Indium Gallium Nitride
Multijunction Solar Cell Performance”, IEEE International Renewable and Sustainable Energy
Conference (IRSEC), pp1-5, 2017.
[15] M. Yamaguchi, “Dislocation Density Reduction in Heteroepitaxial III-V Compound Films on
Si Substrates for Optical Devices”, Journal of Materials Research, vol. 6, pp. 376-384, 1991.
[16] M. Yamaguchi, “Potential and Present Status of III-V/Si Tandem Solar Cells”, In Proc. 40th
IEEE Photovoltaic Spec. Conf., pp. 0821-0826, 2014.
[17] N. Jain and M.K. Hudait, “Design and Modeling of Metamorphic Dual Junction InGaP/GaAs
Solar Cells on Si Substrate for Concentrated Photovoltaic Application”, IEEE Journal of
Photovoltaics, vol. 4, pp. 1683-1689, 2014.
[18] E.G. Tabares, I. Garcia, D. Martin and I.R. Stolle, “Optimizing Bottom Subcells for III-V-on-Si
Multijunction Solar Cells”, In Proc. 37th IEEE Photovoltaic Spec. Conf., pp. 000784-000789,
2011.
[19] S.A. Ringel, J. A. Carlin, T. J. Grassman, B. Galiana, A. M. Carlin, C. Ratcliff, D.
Chmielewski, L. Yang, M.J. Mills, A. Mansouri, S.P. Bremner, A.H. Baillie, X. Hao, H.
Mehrvarz, G. Conibeer and M.A. Green, “Ideal GaP/Si Heterostructures Grown by Mocvd: III-
V/active-Si Subcells, Multijunctions, and Mbe-to- Mocvd III-V/Si Interface Science”, In Proc.
39th IEEE Photovoltaic Spec. Conf., pp. 3383-3388, 2013.
[20] D. Sharma, R. Mehra, B. Raj, “Materials & Methods for Performance Enhancement of
Perovskite Photovoltaic Solar Cells: A Review”, In: Gupta O.H., Sood V.K. (eds) Recent
Advances in Power Systems. Lecture Notes in Electrical Engineering (LNEE), Springer,
Singapore, vol. 699, pp. 531-542, 2021.
[21] T.J. Grassman, J. A. Carlin, B. Galiana, F. Yang, M. J. Mills and S. A. Ringel, “MOCVD-
Grown GaP/Si Subcells for Integrated III- V/Si Multijunction Photovoltaics”, IEEE Journal of
Photovoltaics, vol. 4, no. 3, pp. 972-980, 2014.
[22] S Singh, B Raj, "Design and analysis of hetrojunction Vertical T-shaped Tunnel Field Effect
Transistor", Journal of Electronics Material, Springer, Volume 48, Issue 10, pp 6253–6260,
October 2019.
[23] S Singh, B Raj," Analytical Modeling and Simulation analysis of T-shaped III-V heterojunction
Vertical T-FET”, Superlattices and Microstructures, Elsevier, Vol. 147, PP. 106717, Nov 2020.
[24] T Chawla, M Khosla, B Raj, “Optimization of Double-gate Dual material GeOI-Vertical TFET
for VLSI Circuit Design, IEEE VLSI Circuits and Systems Letter, Vol. 6, issue-2, PP.13-25,
Aug 2020.
[25] M Kaur; N Gupta; S Kumar; B Raj; Arun Kumar Singh, "RF Performance Analysis of
Intercalated Graphene Nanoribbon Based Global Level Interconnects" Journal of
Computational Electronics, Springer, Vol. 19, PP.1002–1013, June 2020.
[26] G Wadhwa, B Raj, "An Analytical Modeling of Charge Plasma based Tunnel Field Effect
Transistor with Impacts of Gate underlap Region" Superlattices and Microstructures, Elsevier,
Vol. 142, PP.106512, June 2020.
[27] S Singh, B Raj,"Modeling and Simulation analysis of SiGe hetrojunction Double GateVertical t-
shaped Tunnel FET”, Superlattices and Microstructures, Elsevier Volume 142, PP.
106496, June 2020.
[28] S Singh, B Raj,"A 2-D Analytical Surface Potential and Drain current Modeling of Double-Gate
Vertical t-shaped Tunnel FET”, Journal of Computational Electronics, Springer, Vol.
19, PP.1154–1163, Apl 2020.
[29] S Singh, S Bala, B Raj, Br Raj," Improved Sensitivity of Dielectric Modulated Junctionless
Transistor for Nanoscale Biosensor Design”, Sensor Letter, ASP, Vol.18, PP.328–333, Apl
2020.
[30] V Kumar, S Kumar and B Raj, “Design and Performance Analysis of ASIC for IoT
Applications” Sensor Letter ASP, Vol. 18, PP. 31–38, Jan 2020.
[31] G Wadhwa, B Raj, "Design and Performance Analysis of Junctionless TFET Biosensor for high
sensitivity" IEEE Nanotechnology, Vol.18, PP. 567 – 574, 2019.
[32] T Wadhera, D Kakkar, G Wadhwa, B Raj, " Recent Advances and Progress in Development of
the Field Effect Transistor Biosensor: A Review" Journal of ELECTRONIC MATERIALS,
Springer, Volume 48, Issue 12, pp 7635–7646, December 2019.