This paper presents the drain current analyses for the different parameters of Nanowire tunnel field-effect transistor (TFET). The device has been designed using an n-channel P+-I-N+ structure for tunneling junction of TFET with gate-all-around (GAA) Nanowire. The gate length has been taken as 100 nm using silicon Nanowire to obtain the various parameters such as ON-current (ION), OFF-current (IOFF), current ratio, and Subthreshold slope (SS) by applying different values of work function at the gate, the radius of Nanowire and oxide thickness of the device. The simulations are performed on Silvaco TCAD which gives a better parametric analysis over conventional tunnel field-effect transistor. The results obtained will be useful for the scientific and research community working in this area.
ratio (ION/IOFF) and SS with the impact of its dimensional parameters such as gate length, oxide thickness and radius of Nanowire.
The structure of designed gate all around Nanowire TFET (NWTFET) is shown in Figure 1. The basic p+-i-n+ structure of TFET is used for device designing with Silicon GAA Nanowire. The basic parameters NWTFET taken as gate length (Lg) = 100 nm, Nanowire Radius (R) = 10 nm, Source/Drain length (Ls/d) = 80 nm, thickness of gate oxide (Tox) = 1.5 nm with Gaussian doping concentration are used for simulation of the device using Silvaco Atlas Tools.
m n 0 8=Ls m n 0 0 1 = Lg m n 0 8=Ls ir A 2 O i S ir A
R=10 nm
A ir S iO 2 A ir
L s = 8 0 n m L g = 1 0 0 n m L s = 8 0 n m Tox=1.5 nm
Tox=1.5 nm maintained under Debye-length; as√([( _ _ )/ + 60. ] ), where as q, N, VT represents the charge of electron, concentration and thermal voltage respectively while refer as dielectric constant [27]. The proposed structure is calibrated with reported conventional TFET structure [19]. The basic parameters of conventional device are taken same as reported in ref [19]. The calibration has been done using plot digitizer tools and Silvaco Simulation Tool. The calibration curve of NWTFET is shown in Figure 2.
The different models have been used for simulations such as BTBT model for tunneling, BGN model for the effect of bandgap and FLDMOB for field-dependent mobility as well as FERMI model for Fermi–Dirac statistics with the addition of CVT model. The used parameter for NWTFET designing is illustrating in Table 1.
The result and simulation of NWTFET are explained in this section by using Silvaco simulation tool. To calculate the different parameters such as drain current, ON/OFF ratio and SS, dimensional parameters has been varied such as gate work-function (ϕg), oxide thickness and radius of Nanowire. The drain current variation of NEFET are observed with the effect/impact of different parameters such as
Firstly, the ID characteristics are observed with different ϕg and taken as 4.0 eV and 4.3 eV shown in Figure 4. For the simulation work the gate voltage varied from -0.2 to 1.2 voltage and drain-source voltage (Vds) taken as 1.2V. According to Figure 4, the maximum ON current (3.60×10-6) and minimum SS (20.25 mV/dec) are observed at ϕg =4.0 eV, but OFF (2.45×10-13) current is also high which leads the SCEs. On the other hand lower OFF current is observed at 4.3 eV. So ϕg =4.3 has been taken for proposed device for minimum SCEs.
Secondly, the ID characteristics are observed with different Tox (1.5 nm and 3.5 nm). Figure 5 illustrates the simulation work of NWTFET on drain current with the impact of different Tox at 1.2V drain-source voltage. It is observed that better parametric value of ID and current ratio with minimum SS (19.40) at Tox=1.5 nm. During the simulation process ϕg , R and Tox has been taken as 4.3 eV, 20 nm and 3.5 nm respectively. The minimum value oxide thickness has given good parametric values and lesser leakage current in the device.
The drain current variation with the effect of nanowire radiu are shown in Figur 6. According to characteristics curve it observed that higher ION (7.63×10-7) at R= 20 nm, but the IOFF current is also higher at this stage. Due to R variation on NWTFET the better SS (15. 22) has been archived on 10 nm. During to simulation work, gate voltage is varied from 0 to 1.5 and Vds=1.2. The detailed observed parametric values are given in Table 2. 4. Conclusion
The device NWTFET has been designed and simulated using Gaussian doping profile and analyzed parametric variations of ION, IOFF, ION/IOFF and SS. The simulated results have also shows the effect on drain-current (Id) with impact of Tox, R and ϕg of the device. The most suitable parametric value are observed such as ION = 3.60x10-6 A/μm, IOFF = 2.95x10-19 A/μm, SS = 15.22 mV/dec and ION/OFF = 6.94×1012. The proposed NWTFET device structure will be suitable for low power applications.
We thank the Group, department of Electronics and Communication Engineering, Dr. B.R. Ambedkar NIT Jalandhar and VLSI Design Group NITTTR Chandigarh for their interest in this work and useful comments to draft the final form of the paper. The support of SERB, Government of India, and Project (EEQ/2018/000444) is gratefully acknowledged. We would like to thank NIT Jalandhar and NITTTR Chandigarh for lab facilities and research environment to carry out this work. 6. References