Impact of Fin Aspect ratio (Tk/Lg) on FinFET Characteristics using Compound gate Dielectrics

Abstract

In FinFET devices, the high-k gate dielectric materials have been considered as alternative to SiO2 for reducing leakage current, diminishing short channel effects and improvingthe effective carrier mobility. In this work, various compound gate dielectric materials have been integrated with 14nm Silicon on insulator FinFET devices. The performance of these structures have been analysed in the term of fin aspect ratio (gate dielectric thickness to gate length). The impact of this ratio on electrical performance parameters of FinFETs at ultra-low power has been deliberated. It has been inspected that the fin aspect ratio for lanthanum doped zirconium oxide has significantly dwindled, SS by 22%, DIBL by 85% , raised ION/IOFFratio in order of 109 andenhanced gmby 1.15 times as contrast to conventional FinFET.

Keywords

• 1 FinFET
• Transconductance
• Subthreshold Swing
• Leakage current
• Dielectric permittivity

1. Introduction

have been achieved [14-16].For future scaled devices, a gate dielectric material withLaZrO2(k= 40) is preferred for below 22nm node FinFET [17-19]. In this work, the different composite high-k gate dielectric materials have been used for designing the 14nm SOI FinFETs. Theelectrical performance of these devices has been analyzed in the term of fin aspect ratiofor 1.1 and 1.6nm gate oxide thickness. This paper is framed as follows: Section 2 explains the description of design of device and simulation framework; Section 3 discusses the device characteristics for digital parameters; last section describes the conclusion of work.

2. Device Structures and Methodology

The three dimensional structures of n-channel FinFETs (NFinFET) for different high-k materials are shown in Figure 1. Table 1 illustrates the NFinFET design parameters [20]. Device simulation is performed with Cogenda Technology Computer Aided Design (TCAD) physical simulator at 300K. The gate dielectric permittivities vary from 3.9 to 40 [ 21, 22 ] and the gate work-functions for all devices are kept at 4.6eV [ 23 ]. The potency of the simulator is examined by matching results of simulated work with published experimental data. It has been observed that our results are in good agreement with Andrade et al. [ 24 ] as shown in Figure 2. Therefore, it shows that the models and parameters used in this paper are valid. The devices have been designed with Drift diffusion model (DDM), Kane’s Model, Lucent Mobility Model and SRH Model[ 25 ]. Figure 3 describes the NFinFET transfer characteristics for Lg=14nm, k= 3.9 to40, Vg=0 to 0.75V and Vd=0.75V.

(a) SOI NFinFET

(b) Devices with different high-k materials ) A (

3. Result and Discussions

The defined range of novel gate oxide materials viz. Silicon nitride (Si3N4, k=7), Aluminium oxide (Al2O3, k=9), Hafnium silicate (HfSiO4, k=11), Yttrium oxide (Y2O3, k=15), Hafnium oxide (HfO2,k=20-25), Niobium pentaoxide (Nb2O5, k=35), and lanthanum doped zirconium oxide (LaZrO2, k=40) are integrated with FinFET device. These materials have high k values (7-40), more energy band gaps, chemically compatible with Si as compared to SiO2. Moreover, these materials can be deposited at high temperature on a silicon active channel using ALD and CVD methods [ 17-19, 26 ].The influence of fin aspect ratio on device characteristics have been demonstrated below using these novel materials. 3.1. Impact of Fin Aspect ratio (Tk/Lg) on Device Characteristics The impact of fin aspect ratios on FinFET’s digital device performance metrics such as Off- current (IOFF) ,current ratio (ION/IOFF),On-current (ION), Drain-induced BarrierLowering(DIBL), Subthreshold swing (SS), transconductance (gm) are discussed through TCAD simulation [ 12, 27-29 ]. The aspect ratio for a given ‘k’ is solved by Tk = { (k

3.9)× Tox } Lg , where Toxis gate oxide thickness, Tk is gate

Lg dielectric thickness, 3.9 is SiO2 dielectric constant and Lg is gate length. The range of k is taken from 3.9 to 40 for gate oxide thickness of 1.1nm and 1.6nm [21].

3.1.1. ION and IOFF currents

3.1.2. DIBL and SS

DIBL signifies the decrease of the cut-in voltage of device at higher drain voltages [12]. SS shows fluctuations in drain current corresponding to gate voltage. The theoretical value of SS is 60mV/dec at 300K. As the gate dielectric permittivity increases, the gate capacitance rises which results in reduced SS and DIBL as shown in Figure 5 [ 12, 30, 31 ].The SS and DIBL for FinFET with LaZrO2 as gate dielectric oxide obtains 10% and 76% reduction for Tox =1.1nm as compared to SiO2 gate oxide material and for Tox =1.6nm the same metrics are declined by 14% and 70% respectively.Lesser DIBL and reduced SS results in low leakage current and better on/off switching performance, respectively [31].

3.1.3. ION/IOFF and Threshold Voltage (Vt)

The Vt is one of the important parameters characterizing the behavior of metal-insulatorsemiconductor interfaces in FinFET structures. To extract the value of Vt, the constant current method is used [32]. The influence of compound gate dielectric permittivity on threshold voltage and the current ratio ION/IOFF as shown in Figure 6 implies that thinner gate oxide (Tox=1.1nm) has higher current ratio and larger Vt as compared to thicker gate oxide (Tox=1.6nm). It is also interesting to note that ION/IOFF is increasing with increasing Vt for both gate oxide thicknesses. An ION/IOFF of order of 109 for higher dielectric gate oxide materials indicates that Vg has greater control over the operation of MOSFET as compared to Vd. Therefore, it is recognized that device with thin gate oxide thickness and high-k gate dielectric permittivity is suitable for the implementation of VLSI circuits [33-35]. 0.26 0.25 )0.24 V (Vt0.23 , eg0.22 a t lo0.21 V ld0.20 o sh0.19 e r hT0.18 0.17

Tox=1.6nm

Tox=1.1nm

3.1.4. Gate Transconductance

The gate transconductance, gm is defined as ratio of drain current variation and gate voltages variation at a constant drain voltage (gm=∂Id /∂Vg). It is expressed in the Siemens unit (S). It is observed that thicker gate oxide has lesser gm as outlined in Figure 7. The highest magnitude of gm decides the gain and operating speed of a transistor [33-35].

4. Conclusion

The impact of fin aspect ratio on the electrical performance of compound gate dielectric based FinFET devices have been analyzed in Cogenda TCAD environment with drift-diffusion transport framework. It is found that the device proposed with higher fin aspect ratio demonstrates superior SCEs immunity. The SS and DIBL for FinFET with lanthanum doped zirconiumas gate dielectric oxide obtains 10% and 76% reduction for Tox =1.1nm as compared to SiO2 gate oxide material and for Tox =1.6nm the same metrics are declined by 14% and 70% respectively. It has been inspected that the fin aspect ratio of LaZrO2 for Tox =1.1nm has significantly dwindled SS by 22% , DIBL by 85%and ION/IOFF is increased in order of 109 over 107 as compared to work done in previous literature [36]. The notable enhancement for gm showsits suitability in VLSI applications as an inverter circuit

5. Acknowledgements References

The authors would like to express our gratitude to Principal, GNDEC, Ludhiana and Dean RIC, I. K. G. P.T.U, Kapurthala for providing help for accomplishment of this work. 3. A.B. Sachid AB, H. Chenming, Little Known Benefit of FinFET over Planar MOSFET in High- Performance Circuits at Advanced Technology Nodes, in : Proceeding of 2012 IEEE International SOI Conference (SOI), NAPA, CA, USA, p.1-2. 4. M. Lapedus . Big Trouble at 3nm -Semiconductor Engineering, https://semiengineering.com/big-trouble-at-3nm; 2018 [accessed 23 August 2019]. 5. A.C. Diebold, Physics Challenges Facing the Semiconductor Industry Based on ITRS. https://www.aps.org/units/fiap/meetings/presentations/upload/diebold.pdf [accessed 23 August 2019]. 6. H. Iwai, Roadmap for 22 nm and beyond, Microelectron Eng. 86 (2009) 1520-1528. 7. S. Stemmer, Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal–oxide–semiconductors. J VacSciTechnol B 22 (2004) 791–800. 8. S.J. Wang, P. C. Lim, A.C.H Huan, C. L. Liu , J. W. Chai, S.Y. Chow , J.S. Pan, Q. Li, C.K. Ong, Reaction of SiO2 with hafnium oxide in low oxygen pressure. ApplPhys Lett 82 (2003) 2047–2049. 9. J. Robertson, High dielectric constant oxides. EurPhys J-ApplPhys 28 (2004) 265–291. 10. S. Park, C.H. Kima, W.J. Lee, S. Sung, M.H. Yoon, Review: Sol-gel metal oxide dielectrics for all-solution-processed electronics”, Material Science Engineering R Reports, 114 (2017)1–22. 11. C. Zhao, T. Witters, B. Brijs, H. Bender, O. Richard, M. Caymax, T. Heeg, J. Schubert, V.V. Afanas’ev, A. Stesmans, D.G. Schlom, Ternary rare-earth metal oxide high-k layers on silicon oxide. ApplPhys Lett 86 (2005)1-3. 12. D. Nirmal D, P. Vijayakumar, P.P.C. Samuel, B.K. Jebalin, N. Mohankumar, Subthreshold analysis of nanoscale FinFETs for ultra-low power application using high-k materials. Int J Electron 100(2012)1–15. 13. Strehlow WH, Cook EL. Compilation of Energy band gaps in elemental and binary compound semiconductors and insulators. Journal of Physical and Chemical Reference Data 2 (1973) 163-199. 14. Y. Yamamoto, K. Kita, K. Kyuno, A. Toriumi, Structural and electrical properties of HfLaOx films for an amorphous high-k gate insulator. Appl. Phys. Lett. 89 (2006) 032903-5. 15. M. Suzuki, M. Tomita, T. Yamaguchi, N. Fukushima, Ultra-thin (EOT) = 3A and low leakage dielectrics of La-aluminate directly on Si substrate fabricated by high temperature deposition, in Proceeding: IEEE International Electron Devices Meeting 2005, Washington, DC, USA .p. 445–8. 16. M. Takahashi, A. Ogawa, A. Hirano, Y. Kamimuta , Y. Watanabe, K. Iwamoto, Gatefirst processed FUSI/HfO2/HfSiOx/Si MOSFETs with EOT = 0.5 nm. in Proceeding: International Electron Devices Meeting Technical Digest 2007, Washington, DC, USA. p. 523–6. 17. J. M. Gaskell, A.C. Jones, H.C. Aspinall, S. Taylor, P. Taechakumput, P.R. Chalker, P.N. Heys, R.C. Odedra, Deposition of lanthanum zirconium oxide high- κ films by liquid injection atomic layer deposition. Appl. Phys. Lett. 91 (2007) 112912 -1 to 3. 18. C. Zhao, C.Z. Zhao, M. Werner, S. Taylor, P.R. Chalker, Review Article Advanced

CMOS Gate Stack: Present Research Progress. ISRN Nanotechnology (2012) 1-35. 19. L.N. Liu, W. M.Tang, P.T. Lai, Review: Advances in La-Based High-k Dielectrics for

MOS Applications. Coatings 9 (2019)1-30 . 20. Cogenda User’s Guides. http://www.cogenda.com/article/downloads[accessed 27

August 2019]. 21. G Wadhwa, B Raj, "Design and Performance Analysis of Junctionless TFET

Biosensor for high sensitivity" IEEE Nanotechnology, Vol.18, PP. 567 – 574, 2019.

References

1. P. Gargini , ITRS Past, Present and Future, http://www.itrs2.net/itrs-reports. html; 2015 [accessed 23 August 2019 ].

2. J.P. Colinge , FinFETs and other Multi-Gate Transistors . Integrated Circuits and Systems Series , New York, USA : Springer Science+ Bussiness Media; 2008 .

22. T Wadhera , D Kakkar , G Wadhwa , B Raj , " Recent Advances and Progress in Development of the Field Effect Transistor Biosensor: A Review" Journal of ELECTRONIC MATERIALS , Springer, Volume 48 , Issue 12, pp 7635 - 7646 , December 2019 .

23. S Singh , B Raj , "Design and analysis of hetrojunction Vertical T-shaped Tunnel Field Effect Transistor" , Journal of Electronics Material , Springer, Volume 48 , Issue 10, pp 6253 - 6260 , October 2019 .

24. C Goyal , J S Ubhi and B Raj , “A Low Leakage CNTFET based Inexact Full Adder for Low Power Image Processing Applications” , International Journal of Circuit Theory and Applications , Wiley, Volume47, Issue9, Pages 1446 -1458, September 2019 .

25. Sharma , S. K.., Raj , B. , Khosla , M. , "Enhanced Photosensivity of Highly Spectrum Selective Cylindrical Gate In1-xGaxAs Nanowire MOSFET Photodetector , Modern Physics letter-B , Vol. 33 , No. 12, PP. 1950144 ( 2019 ).

26. J Singh , B Raj , “Design and Investigation of 7T2M NVSARM with Enhanced Stability and Temperature Impact on Store/Restore Energy” , IEEE Transactions on Very Large Scale Integration Systems , Vol. 27 , Issure 6 , PP. 1322 - 1328 June 2019 .

27. A K Bhardwaj , S Gupta , B Raj , Amandeep Singh, “ Impact of Double Gate Geometry on the Performance of Carbon Nanotube Field Effect Transistor Structures for Low Power Digital Design”, Computational and Theoretical Nanoscience , ASP , Vol. 16 , PP. 1813 - 1820 , 2019 .

28. C Goyal , J SUbhi and B Raj , Low Leakage Zero Ground Noise Nanoscale Full Adder using Source Biasing Technique , “Journal of Nanoelectronics and Optoelectronics” , American Scientific Publishers, Vol. 14 , PP. 360 - 370 , March 2019 .

29. A Singh , M Khosla , B Raj , “Design and Analysis of Dynamically Configurable Electrostatic Doped Carbon Nanotube Tunnel FET" ,” Microelectronics Journal, Elesvier , Volume 85 , Pages 17-24, March 2019 .

30. G Wadhwa , B Raj , "Label Free Detection of Biomolecules using Charge-Plasma-Based Gate Underlap Dielectric Modulated Junctionless TFET" Journal of Electronic Materials (JEMS) , Springer, Volume 47 , Issue 8, pp 4683 - 4693 , August 2018