Impact of Fin Aspect ratio (Tk/Lg) on FinFET Characteristics using Compound gate Dielectrics Gurpurneet Kaur1, Sandeep S. Gill2, Munish Rattan3 and Navneet Kaur4 1 Electronics Engineering, I.K.G.P.T.U, Kapurthala, Punjab 144603, India. 2 Electronics & Communication Engineering, NITTTR, Chandigarh, Punjab, 160019, India. 3,4 Electronics & Communication Engineering, GNDEC, Ludhiana, Punjab 141006, India Abstract In FinFET devices, the high-k gate dielectric materials have been considered as alternative to SiO2 for reducing leakage current, diminishing short channel effects and improvingthe effective carrier mobility. In this work, various compound gate dielectric materials have been integrated with 14nm Silicon on insulator FinFET devices. The performance of these structures have been analysed in the term of fin aspect ratio (gate dielectric thickness to gate length). The impact of this ratio on electrical performance parameters of FinFETs at ultra-low power has been deliberated. It has been inspected that the fin aspect ratio for lanthanum doped zirconium oxide has significantly dwindled, SS by 22%, DIBL by 85% , raised ION/IOFFratio in order of 109 andenhanced gmby 1.15 times as contrast to conventional FinFET. Keywords 1 FinFET, Transconductance, Subthreshold Swing, Leakage current, Dielectric permittivity. 1. Introduction Nowadays, several miniature devices have been devised to meet the need of industry oriented applications such as higher speed transistors with low power consumption. It was inspected that FinFET device shows noticeable reduction in short channels, utilized less power and improves switching activity compared to other devices [1-3]. In transistor manufacturing processes, the several semiconductor industries such as Intel, IBM, Samsung, and TSMC has started using high-k gate oxide and metallic gate materials for scaled devices. According to ITRS reports, the scaling of gate dielectric material, SiO2 (k=3.9) below 2nm has resulted in high leakage current due to generation of direct tunneling gate off- current [4-6]. Therefore, for prevention of this negative effect in sub-22nm technology, various novel materials such as Al2O3 (k=9), ZrO2 and HfO2 (k=25), Ta2O5 (22) and CeO2 (23-26) have been widely used in microelectronic devices. The important properties of these insulating materials involve high energy band gap,chemically compatible with Silicon and high crystallization temperatures. The energy band-gap of few materials such as SiO2 (9eV), Al2O3 (6eV), HfO2 (6eV), La2O3 (5.18eV) and ZrO2 (5.8eV) have been lying in the range of 4-12eV [7-13]. The good electrical characteristics using La2Hf2O7 (LHO) high-k dielectric in place of SiO2 has been proved as prominent candidate. Excellent transistors with enhanced performance based on Hafnium based gate dielectrics as the insulation layers International Conference on Emerging Technologies: AI, IoT, and CPS for Science & Technology Applications, September 06–07, 2021, NITTTR Chandigarh, India EMAIL: gurpurneetkaur@gmail.com (A. 1); ssg@nitttrchd.ac.in (A. 2); dr.munishrattan@gmail.com (A. 3); navkaur1588@gmail.com (A. 4) ©2021 Copyright for this paper by its authors. Use permitted under Creative Commons License Attribution 4.0 International (CC BY 4.0). CEUR Workshop Proceedings (CEUR-WS.org) have been achieved [14-16].For future scaled devices, a gate dielectric material withLaZrO2(k= 40) is preferred for below 22nm node FinFET [17-19]. In this work, the different composite high-k gate dielectric materials have been used for designing the 14nm SOI FinFETs. Theelectrical performance of these devices has been analyzed in the term of fin aspect ratiofor 1.1 and 1.6nm gate oxide thickness. This paper is framed as follows: Section 2 explains the description of design of device and simulation framework; Section 3 discusses the device characteristics for digital parameters; last section describes the conclusion of work. 2. Device Structures and Methodology The three dimensional structures of n-channel FinFETs (NFinFET) for different high-k materials are shown in Figure 1. Table 1 illustrates the NFinFET design parameters [20]. Device simulation is performed with Cogenda Technology Computer Aided Design (TCAD) physical simulator at 300K. The gate dielectric permittivities vary from 3.9 to 40 [21, 22] and the gate work-functions for all devices are kept at 4.6eV [23]. The potency of the simulator is examined by matching results of simulated work with published experimental data. It has been observed that our results are in good agreement with Andrade et al. [24] as shown in Figure 2. Therefore, it shows that the models and parameters used in this paper are valid. The devices have been designed with Drift diffusion model (DDM), Kane’s Model, Lucent Mobility Model and SRH Model[25]. Figure 3 describes the NFinFET transfer characteristics for Lg=14nm, k= 3.9 to40, Vg=0 to 0.75V and Vd=0.75V. (a) SOI NFinFET (b) Devices with different high-k materials Figure 1: Structure of SOI NFinFET for different high-k materials 10-5 Reference [24] Proposed Work 10-6 Drain Current, Id (A) 10-7 Vd= 50mV 10-8 Lg= 180nm WFin= 130nm 10-9 HFin = 65nm 10-10 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Gate Voltage, Vg (V) Figure 2: Transfer characteristics of proposed FINFET and reference FinFET [24] Table 1:NFinFET design parameters Device’s Performance Proposed device(NFinFET) Parameters Length gate terminal, Lg(nm) 14 Fin Pitch of transistor (nm) 42 Fin Width of transistor (nm) 8 Fin Height of transistor (nm) 24 Work function of gate 4.6 terminal (eV) Gate dielectric permittivity , k 3.9 - 40 Physical Oxide Thickness(nm) 1.1,1.6 Supply Voltage (Volts) 0.75 50µ Tk/Lg(0.8) Lg= 14nm Drain Current, Id (A) Tk/Lg(0.7) Tk/Lg(0.6) Tox=1.1nm 40µ Tk/Lg(0.5) FIN= 24nm Tk/Lg(0.4) WFIN= 8nm 30µ Tk/Lg(0.3) Vd=0.75V Tk/Lg(0.22) Tk/Lg(0.18) 20µ Tk/Lg(0.14) Tk/Lg(0.07) 10µ 0 0.32 0.40 0.48 0.56 0.64 0.72 Gate Voltage, Vg (V) Figure 3: NFinFET Transfer characteristics for Lg=14nm, k =3.9 to 40, Vg= 0 to 0.75V and Vd=0.75V. 3. Result and Discussions The defined range of novel gate oxide materials viz. Silicon nitride (Si3N4, k=7), Aluminium oxide (Al2O3, k=9), Hafnium silicate (HfSiO4, k=11), Yttrium oxide (Y2O3, k=15), Hafnium oxide (HfO2,k=20-25), Niobium pentaoxide (Nb2O5, k=35), and lanthanum doped zirconium oxide (LaZrO2, k=40) are integrated with FinFET device. These materials have high k values (7-40), more energy band gaps, chemically compatible with Si as compared to SiO2. Moreover, these materials can be deposited at high temperature on a silicon active channel using ALD and CVD methods [17-19, 26].The influence of fin aspect ratio on device characteristics have been demonstrated below using these novel materials. 3.1. Impact of Fin Aspect ratio (Tk/Lg) on Device Characteristics The impact of fin aspect ratios on FinFET’s digital device performance metrics such as Off- current (IOFF) ,current ratio (ION/IOFF),On-current (ION), Drain-induced BarrierLowering(DIBL), Subthreshold swing (SS), transconductance (gm) are discussed through TCAD simulation [12, 27-29]. The aspect ratio for a given ‘k’ is solved by Tk L = g { (k 3.9) × T } L , where T is gate oxide thickness, T is gate ox g ox k dielectric thickness, 3.9 is SiO2 dielectric constant and Lg is gate length. The range of k is taken from 3.9 to 40 for gate oxide thickness of 1.1nm and 1.6nm [21]. 3.1.1. ION and IOFF currents Figure 4 (a-b) demonstrates that on-current (calculated at Vg=Vd=0.75V) enhances and off-current (determined at Vg=0, Vd=0.75V) reduces with the increase in aspect ratio. Furthermore, on-current and off-current improvement is more for Tox =1.1nm as compared to Tox =1.6nm. This is convenient to understand, as the narrow gate oxide has greater command over the channel region and thereby superior performance at short channel [18, 30]. The maximum on-current and minimum off-current is obtained for highest Tk/Lg ratio (k=40, LaZrO2). 2.00E-012 0.000050 1.80E-012 Off-Current , IOFF (A) Tox=1.1nm Tox=1.6nm Lg= 14nm 0.000045 Tox=1.6nm 1.60E-012 Tox=1.1nm HFIN= 24nm On-Current, ION (A) 0.000040 1.40E-012 WFIN= 8nm Lg= 14nm 1.20E-012 0.000035 Vd=Vg=0.75V HFIN= 24nm 1.00E-012 0.000030 8.00E-013 WF= 4.6eV WFIN= 8nm 0.000025 Vd=Vg=0.75V 6.00E-013 0.000020 WF= 4.6eV 4.00E-013 2.00E-013 0.000015 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Tk/Lg Tk/Lg (a) (b) Figure 4. The influence of compound gate dielectric on (a) ION and (b) IOFF for oxide thickness of 1.1nm and 1.6nm. (Fin aspect ratio is calculated as Tk/Lg= (k/3.9)*(1.1 or 1.6)*(1/14). 3.1.2. DIBL and SS DIBL signifies the decrease of the cut-in voltage of device at higher drain voltages [12]. SS shows fluctuations in drain current corresponding to gate voltage. The theoretical value of SS is 60mV/dec at 300K. As the gate dielectric permittivity increases, the gate capacitance rises which results in reduced SS and DIBL as shown in Figure 5 [12, 30, 31].The SS and DIBL for FinFET with LaZrO2 as gate dielectric oxide obtains 10% and 76% reduction for Tox =1.1nm as compared to SiO2 gate oxide material and for Tox =1.6nm the same metrics are declined by 14% and 70% respectively.Lesser DIBL and reduced SS results in low leakage current and better on/off switching performance, respectively [31]. 72 TOX (1.1nm) Subthreshold Swing, SS (mV/dec) Tox=1.6nm 60 TOX (1.6nm) 70 Tox=1.1nm Lg= 14nm 50 HFIN= 24nm Lg= 14nm 68 DIBL(mV/V) WFIN= 8nm 40 HFIN= 24nm 66 Vd=Vg=0.75V WFIN= 8nm 30 WF= 4.6eV Vd=Vg=0.75V 64 20 WF= 4.6eV 62 10 60 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Tk/Lg Tk/Lg (a) (b) Figure 5. Influence of aspect ratio (Tk/Lg) of given k dielectric permittivity on (a) SS and (b) DIBL for oxide thickness of 1.1nm and 1.6nm. 3.1.3. ION/IOFF and Threshold Voltage (Vt) The Vt is one of the important parameters characterizing the behavior of metal-insulator- semiconductor interfaces in FinFET structures. To extract the value of Vt, the constant current method is used [32]. The influence of compound gate dielectric permittivity on threshold voltage and the current ratio ION/IOFF as shown in Figure 6 implies that thinner gate oxide (Tox=1.1nm) has higher current ratio and larger Vt as compared to thicker gate oxide (Tox=1.6nm). It is also interesting to note that ION/IOFF is increasing with increasing Vt for both gate oxide thicknesses. An ION/IOFF of order of 109 for higher dielectric gate oxide materials indicates that Vg has greater control over the operation of MOSFET as compared to Vd. Therefore, it is recognized that device with thin gate oxide thickness and high-k gate dielectric permittivity is suitable for the implementation of VLSI circuits [33-35]. 0.26 0.25 1.4x109 Tox=1.6nm On-current/Off-current 0.24 1.2x109 Threshold Voltage,Vt (V) Tox=1.1nm Tox=1.6nm 0.23 1.0x109 Tox=1.1nm 0.22 Lg= 14nm 8.0x108 Lg= 14nm 0.21 HFIN= 24nm 6.0x108 HFIN= 24nm 0.20 WFIN= 8nm 4.0x108 WFIN= 8nm 0.19 Vd=Vg=0.75V Vd=Vg=0.75V 2.0x108 0.18 WF= 4.6eV WF= 4.6eV 0.0 0.17 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Tk/Lg Tk/Lg (a) (b) Figure 6. Dependence of (a) Vt and (b) ION/IOFF on the aspect ratio (Tk/Lg) for varied k of 1.1nm and 1.6nm gate oxide thickness. 3.1.4. Gate Transconductance The gate transconductance, gm is defined as ratio of drain current variation and gate voltages variation at a constant drain voltage (gm=∂Id /∂Vg). It is expressed in the Siemens unit (S). It is observed that thicker gate oxide has lesser gm as outlined in Figure 7. The highest magnitude of gm decides the gain and operating speed of a transistor [33-35]. Transconductance, gm(S) 60.0µ Tk/Lg(0.8) Lg= 14nm Tk/Lg(0.7) Tox=1.1nm 50.0µ Tk/Lg(0.6) Tk/Lg(0.5) FIN= 24nm 40.0µ Tk/Lg(0.4) WFIN= 8nm Tk/Lg(0.3) Vd=0.75V 30.0µ Tk/Lg(0.22) Tk/Lg(0.18) 20.0µ Tk/Lg(0.14) Tk/Lg(0.07) 10.0µ 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Gate Voltage, Vg (V) Figure 7: Transconductance trend for variable dielectric permittivity (k) of Tox=1.1nm. 4. Conclusion The impact of fin aspect ratio on the electrical performance of compound gate dielectric based FinFET devices have been analyzed in Cogenda TCAD environment with drift-diffusion transport framework. It is found that the device proposed with higher fin aspect ratio demonstrates superior SCEs immunity. The SS and DIBL for FinFET with lanthanum doped zirconiumas gate dielectric oxide obtains 10% and 76% reduction for Tox =1.1nm as compared to SiO2 gate oxide material and for Tox =1.6nm the same metrics are declined by 14% and 70% respectively. It has been inspected that the fin aspect ratio of LaZrO2 for Tox =1.1nm has significantly dwindled SS by 22% , DIBL by 85%and ION/IOFF is increased in order of 109 over 107 as compared to work done in previous literature [36]. The notable enhancement for gm showsits suitability in VLSI applications as an inverter circuit 5. Acknowledgements The authors would like to express our gratitude to Principal, GNDEC, Ludhiana and Dean RIC, I. K. G. P.T.U, Kapurthala for providing help for accomplishment of this work. References 1. P. Gargini, ITRS Past, Present and Future, http://www.itrs2.net/itrs-reports.html; 2015 [accessed 23 August 2019]. 2. J.P. Colinge, FinFETs and other Multi-Gate Transistors. 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