In this paper, the authors propose a parallel Digital Direct Synthesis (DDS) suitable for digital ultra wide-band systems. The proposed architecture ofers the possibility to generate sine and/or cosine waves with a user-defined level of parallelism without the necessity to increase the clock frequency. It has been designed in SIMULINK coded in VHDL at RTL level and finally implemented on a Xilinx FPGA. Synthesis and place & route have been performed using the XILINX VIVADO toolchain. Results are provided in terms of hardware resources, speed, and power consumption considering a level of parallelism equal to 4. Implementation results show a low area complexity and very reduced power consumption that coupled with the flexibility in terms of parallelism level make this DDS useful in ultrawideband low-power systems. In particular, the DDS is characterized by an energy per operation of about 91 pJ. The reduced hardware complexity allows its implementation on low-cost FPGA.
garding the parallelization of convolution-based systems
as FIR filters and farrow filters. However, in order to
In the last few years, digital communications found appli- use these convolution-based systems on communication
cations in always more fields [
Splitting data on parallel datapaths make it possible to It has been characterized in terms of speed, area, and process data to a reduced clock frequency maintaining power consumption The paper is structured as follow: in unaltered the total sample rate that is the sum of the Sect. 2 the architecture of the proposed DDS is discussed sample rate of the single sub-data path. after after a brief general discussion on DDS. In Sect. 3
Although this new paradigm ofers advantages in terms the FPGA implementation of the proposed architecture
of processing rate and consequently bandwidth, it re- is discussed. In Sect. 4 the experimental results in terms
quires the re-engineering of processing architectures that of hardware complexity, speed and power are show and
must be repeated in order to be able to process parallel ifnally in Sect. 5 conclusions are provided.
frames of data [
where K is the tuning word, is the system clock
frequency and finally 2 is the number of samples used
to represent a sine/cosine period inside the ROM. More
details about the DDS architecture are shown in [
In Fig. 2 is shown the block diagram of a parallel DDS with a level of parallelism equal to N, able to generate a frame-based sine /cosine wave.
The main diferences with a traditional DDS as the one shown in Fig.1 is the presence of N LUT and a Frame Address Generator (FAG).
The N LUTs are required for the simultaneous generation of N sine/cosine waves because although all the LUTs contain the same samples, it is not possible to read N data in parallel using a single LUT.
The FAG computes the N addresses necessary to read the N samples in parallel. where Ph is the output of the phase generator.
been implemented on a XILINX FPGA. Thanks to their
high computation capabilities and their flexibility, FPGAs
are used in always more application fields as for example,
communication, video processing, Machine Learning [
FPGAs are widely used in systems that require high computing power. In this context, they can also be a powerful and valuable ally for blockchain technology.
For instance, [22] aimed to “certify the data” without the need for a centralized organization using blockchain.
Indeed, in order for a blockchain system to be feasible in terms of scalability, interoperability and sustainability, complex cryptographic operations that require speed and power must be performed on a dedicated accelerator tivity for any node of the synthesized circuit and allow an system (FPGA). accurate estimation of the dynamic power consumption.
The proposed system has been simulated and validated In fact, as known from the theory the dynamic power through MATLAB/SIMULINK simulations. Generated consumption need knowledge on the switching activity waveforms have been compared with the ones generated to be accurate estimated [23]. by a traditional DDS in order to assure the efective operation of the system. Simulations show that the proposed 4 channel parallel DDS doe not introduce any decrease in 4. Experimental Results the Spurious-Free Dynamic Range SFDR. The datapath has been maintained at 10 bits without any truncations. After the synthesis and the Place & Route, the proposed
After the MATLAB/SIMULINK simulations, the pro- DDS has been characterized in terms of hardware composed DDS has been coded in VHDL at behavioral level. plexity, speed and power consumption. Nowadays power For what concerns the LUTs, they have been implemented consumption represents a very crucial aspect, especially using the XILINX IP cores through BLOCK RAMs. In or- for embedded systems that not always are connected der to do this, we previously sample sine waves in MAT- with the power supply but are always more powered by LAB. The sine wave has been sampled with 210 samples batteries or energy harvesting systems. In these cases, using a fixed-point representation with 10 bit. in fact, the power consumption (and consequently the
Test benches have been performed through the XILINX energy consumption) must be reduced to the maximum ISIM simulator. Synthesis and Place and route have been in order to prolong the life of the battery. performed using the XILINX VIVADO tool-chain. Power The FPGA resources used for the implementation of estimation has been performed through post-implementationthe proposed DDS are shown in Tab. 1. simulation taking into account the real switching activ- As possible to see, the FPGA resources required for the ity of the circuit. This was possible using the Switching proposed DDS implementation are very reduced. This Activity Interchange Format (SAIF) files in the phase of allows having enough resources on the FPGA to implepower estimation. These files contain the switching ac- ment also other systems. This aspect is very important because modern FPGA-based communication systems require always more the presence of complex elements as for example machine learning systems or DSP systems [24, 25? ].
In order to evaluate the max-speed of the proposed architecture, we performed several syntheses and Place & Route using diferent timing constraints. The maximum frequency available by our architecture is 385 MHz.
Such as frequency allows reaching a total sample rate of 4* 385=1.540 GHz. Considering what is established by the sampling theory, this frequency allows the generation of sine waveforms up to 770 MHz This frequency can be increased by incrementing the parallelism level of the DDS.
The average dynamic power consumption measured at 385 MHz is 140 mW. By definition the energy per operation is defined as eq. 3.
() ∫︁
() where is the time require to execute the operation.
/4 where is the clock period equal to 2.6 ns and consequently = /4 = 0.65 ns.
For discrete time systems eq.3 can be rewritten as: = ∑︁ * where is the average power consumption that in our case is 140 mW.
According eq. 4 the energy (dynamic) per operation (sine sample computation) is equal to 91 pJ.
(4) work with wide-band signals. The parallelization ofers the possibility to manage wide-band signals without the necessity to increase the clock frequency. In order to evaluate the proposed architecture, we firstly simulate it in MATLAB/SIMULINK, and in a second phase, after a ifxed point analysis, we code it in VHDL and implement it on a XILINX FPGA.
Experimental results show a very reduced hardware complexity and very reduced power consumption that represents a very important aspect in embedded systems characterized by the absence of a connection with the power grid.