=Paper=
{{Paper
|id=Vol-3126/paper44
|storemode=property
|title=Design of ternary decoder
|pdfUrl=https://ceur-ws.org/Vol-3126/paper44.pdf
|volume=Vol-3126
|authors=Larysa Martynovych,Yurii Gunchenko,Yurii Shugailo,Yurii Bercov,Dmytro Slutskyi,Kostiantyn Smirnov
}}
==Design of ternary decoder==
<pdf width="1500px">https://ceur-ws.org/Vol-3126/paper44.pdf</pdf>
<pre>
Design of Ternary Decoder
Larysa Martynovych1 , Yurii Gunchenko2, Yurii Shugailo 3, Yurii Bercov 4 Dmytro Slutskyi5,
Kostiantyn Smirnov 6
1,2,3,4,6
        I.I.Mechnykov Odesa National University, Dvoryanska str, 2, Odesa, 65082, Ukraine
5
    Odesa National Maritime University. Mechnikova str, 34 Odesa, 65000, Ukraine

                  Abstract
                  The analysis of advantages of ternary logic on an example of construction of ternary RS-trigger
                  is considered. Based on the multi-threshold element of multi-valued logic (MTEML), the
                  structures of the different variants of single-input decoders with the different active levels are
                  proposed. The structures of the obtained elements and their schemes for the selection of the
                  simplest variants are analyzed.
                  The future directions of work and expediency of development of subjects of construction of
                  ternary elements and systems on their basis are outlined.

                  Keywords 1
                  Ternary logic, multi-threshold element of multi-valued logic, methods of constructing ternary
                  elements, decoder


1. Introduction                                                                               example, the ratio A> B, A≤B (Fig. 2). It is clear
                                                                                              that binary scales are less convenient than ternary.
                                                                                              Only in the case of A> B the result of weighing on
   The relevance of the topic is due to the fact that
                                                                                              them is determined immediately, and in the other
modern computer technology needs new ways to
                                                                                              two cases it is necessary to re-weigh by swapping
increase computing power and speed. Binary
                                                                                              A and B [2].
logic is now the most common, but it has a
number of disadvantages that can be eliminated
through the use of ternary logic, including
increasing the range of numbers, speeding up
operations, reducing the amount of equipment.
   The purpose of the work is the design and
synthesis of logical elements for ternary computer
systems.
   Three-valued logic is more convenient and
familiar to people than two-valued logic [1].
Consider some examples that prove this.                                                       Figure 1: Ternary scales
   The first example is the weight of the levers
(Fig. 1). They are a characteristic ternary device,
the three states of which correspond to three
possible relations: A> B, A = B, A <B. For
comparison, consider also the executive scales,
which can take only two states, corresponding, for

ISIT 2021: II International Scientific and Practical Conference
«Intellectual Systems and Information Technologies», September
13–19, 2021, Odesa, Ukraine
EMAIL:          larysa.yaroslavna@gmail.com        (A.       1);
gunchenko@onu.edu.ua (A. 2), y.shugailo@gmail.com (A. 3);
bercov@gmail.com (A. 4); gunchenko@onu.edu.ua (A. 5)
ORCID: 0000-0001-7351-1467 (A. 1); 0000-0003-4423-8267 (A.
2); 0000-0003-2144-0930 (A. 3); 0000-0001-9704-1121 (A. 4);
0000-0003-3734-9460 (A. 5); 0000-0001-6813-0109 (A. 6).
              ©️ 2021 Copyright for this paper by its authors. Use permitted under Creative
              Commons License Attribution 4.0 International (CC BY 4.0).
              CEUR Workshop Proceedings (CEUR-WS.org)
                                                               in the three-input ternary adder the
                                                           transfer to the next category occurs in 8
                                                           situations out of 27, and in the binary adder -
                                                           in 4 out of 8;
                                                               the three-level signal is more resistant to
                                                           interference in transmission lines. This means
                                                           that special methods of redundant coding of
Figure 2: Binary scales                                    ternary information are simpler than binary
                                                           [7].
    The next example is branching by the sign of
the variable x (Fig. 3). This example demonstrates
the fundamental difference between three-digit          2. Ternary RS-trigger
logic and two-digit logic. It is that one and the
same can be represented in a more compact form              In addition to combinational circuits, the
in ternary logic than in binary. In this example, the   output state of which at each time depends on the
ternary branching by the sign x is described by         set of input signals, in computer systems are
specifying a single three-digit operation sign (x)      widely used circuits and nodes in which the output
and is performed in one step, while the same            state depends not only on the input signals but also
branching, which is carried out by means of two-        on their previous state, ie digital automata. As you
digit logic, associated with the need for two           know, the simplest device with two stable states
operations and is performed by two steps. Such          at the output - the trigger is often used to store
branching algorithms are often used in decision-        information.
making systems, in "Smart Homes" to process                 Consider binary and ternary RS-flip-flops in
signals from sensors and the corresponding              comparison.
response to them. Ternary logic in this case will           Figure 4 shows the designation of the binary
significantly accelerate this reaction [3].             RS-flip-flop.




                                                        Figure 4: Designation of a binary RS-trigger

             a)                 b)                          The trigger has 2 states Q = 0 and Q = 1, which
Figure 3: Branch operation by sign: a) ternary          are displayed on its outputs. The next state of the
scheme; b) binary scheme                                trigger depends on the current state and the
                                                        combination of input signals at its two inputs.
   These examples show that ternary logic allows            It is known that it has a forbidden combination
you to reason more simply and more quickly than         of input signals. If there are active signals S = 1,
reasoning in terms of ambiguous logic [4]. In           R = 1 on both inputs at the same time, this mode
practice, people probably use mostly ternary logic      is considered forbidden, because the state of the
[5,6].                                                  trigger will not be determined.
   Some properties of ternary logic determine its           In ternary logic, three allowed modes can be
effectiveness and practical value:                      provided with only one input [8]. In this case, in
       the branching command by sign takes             addition to reducing the number of pins, such a
   twice less time than in binary;                      device in principle cannot be the fourth, forbidden
       the ternary adder subtracts when inverting      mode. Based on MTEML the ternary RS -trigger
   one of the terms, from which it follows that the     which scheme is shown in fig. 5.
   ternary counter is automatically reversible;
                                                        states of output signals, i.e. nine combinations,
                                                        which are represented by terms in the table. The
                                                        input signal is denoted by X, the signals of the
                                                        current state and their sum - the current state are
                                                        denoted by lowercase letters -r, + r, q,
                                                        respectively. The signal that is directly generated
                                                        at the input of the trigger is equal to the sum of
                                                        these signals and is indicated in the table by
                                                        column X; -r; + r, this signal determines the next
                                                        combination of output signals -R, + R and the next
                                                        state Q = -R; + R, which trigger will go.
Figure 5: Scheme of ternary RS-trigger

    Feedback from the + R, -R outputs provides          3. Ternary single-input decoders
support for the current state of the trigger in the
absence or zero value of the input signal. The
input signal "+" leads to the transition of the             Decoders are a must-have for any computer
                                                        system. They are more commonly used to identify
trigger to the state "+", the signal "-" to the
                                                        address space and are used to select specific
transition to the corresponding state "-". The
                                                        devices or memory cells when addressing them
ternary RS-flip-flop has another state "0", but it is
                                                        (setting the address on the appropriate bus).
unstable and is possible only when the system is
initially turned on (Table 1).                              In fact, decoders convert the input code of a
                                                        given number system to unary, in which the
    When applied to the input x = 0 - the trigger is
                                                        output active signal is present only on one of the
in storage mode, its state does not change. When
                                                        outputs, the number of which corresponds to the
applied to the input x = - 1 (minus) the trigger goes
                                                        input combination. The maximum number of
into reset mode, ie the output will also be minus
1, when x = + 1 the trigger goes into installation      outputs for a ternary decoder is m = 3n, where n is
                                                        the number of inputs. Consider the construction of
mode and the output is also +1. The state of the
trigger, when the signal at its output is zero, and     one- and two-input ternary decoders.
                                                            For a single-input decoder, the number of
the input is a non-zero value (either "+" or "-") is
                                                        outputs is three. Depending on what value of
unstable, and immediately changes depending on
the signal sign. Table 1 shows the previous and         output signals we will consider active, and what
                                                        passive - there can be six different combinations
subsequent states of the trigger.
                                                        and, accordingly, schemes of construction of one-
                                                        bit ternary decoders. To build decoders we use
Table 1
                                                        MTEML. The table 2 shows the values of the
Truth table of the ternary RS-trigger
                                                        outputs of the element depending on the signal at
 №      Х     -r +r    q     X; – -R1         Q=        the input X.
                             r; +r +R1        -R1;
                                              +R1       Table 2
  0     –     – 0       –      - -    –   0    –        Values of the outputs of the MTEML
  1     –     – +       0       –     –   0    –            X         -L     -R       +L           +R
  2     –     0 +       +       0     –   +    0             -        0       -        +            0
  3     0     – 0       –       –     –   0    –            0         0       -        0            +
  4     0     – +       0       0     –   +    0            +          -      0        0            +
  5     0     0 +       +       +     0   +    +
  6     +     – 0       –       0     –   +    0
                                                           On the basis of MTEML variants of a ternary
  7     +     – +       0       +     0   +    +        one-input decoder with various active signals
  8     +     0 +       +     + +     0   +    +        which structural schemes are shown in fig. 6-11.
  0     –     – 0       –      --     –   0    –
  1     –     – +       0       –     –   0    –           Consider a decoder whose active value is "-",
                                                        passive value "0". The truth table for each of the
   In principle, a ternary RS-flip-flop can have        three outputs is presented in the table 3.
three different states of input and three different
Table 3
Decoder truth table
     X          Y0            Y1            Y2
      -          -            0             0
     0           0             -            0
     +           0            0              -

   It is easy to conclude that to obtain three output
signals you need to combine the following outputs
of MTEML:                                               Figure 7: Block diagram of a single-input decoder
   Y0= -R, +R, -L = -1, +R                              with active "-"
   Y1= -R, +L
   Y2=-L                                                   Tables 5 - 8 show the output signals for the
   To simplify the implementation of the outputs        cases of active "0", passive "-" (Table 5), active
-R, -L, which are equal to "-1", regardless of the      "0", passive "+" (Table 6), active "-", passive "+"
input signal, replace the corresponding current         ( Table 7) and active “+”, passive “-” (Table 8).
source. We obtain the scheme shown in Fig. 6.              Figures 8 - 11 show the implementation
                                                        schemes for all these cases.

                                                        Table 5
                                                        Decoder truth table. Active signal "0"
                                                             X          Y0           Y1            Y2
                                                              -          0            -             -
                                                             0           -            0             -
                                                             +           -            -            0

                                                           Y0= -L, -R, +L = -1, +L
                                                           Y1= -L, -R, +R, -L = -1, +R, -L
Figure 6: Block diagram of a single-input decoder          Y2= -R
with active "-"

   The following truth table (Table 4) shows the
case of the active signal "+", passive "0".

Table 4
Decoder truth table
     X          Y0            Y1            Y2
      -          +            0             0
     0           0            +             0
     +           0            0             +

   The following are expressions for constructing
outputs by combining and simplifying the                Figure 8: Block diagram of a single-input decoder
corresponding signals. In fig. 7 shows a diagram        with active "0", passive "-"
that implements this.
   Y0= +L                                               Table 6
   Y1= +R, -L                                           Decoder truth table
   Y2= +R, -R, +L = +1, -R
                                                             X          Y0           Y1            Y2
                                                              -          0           +             +
                                                             0           +           0             +
                                                             +           +           +             0
                                                    Table 8
   Y0= +R                                           Decoder truth table Active signal "+"
   Y1= +L, +R, -R, +L = +1, -R, +L                       X          Y0           Y1            Y2
   Y2= +L, +R, -L = +1, -L
                                                          -          +            -             -
                                                         0           -           +              -
                                                         +           -            -            +

                                                       Y0= -1, +L, +L
                                                       Y1= -1, +R, +R, -L, -L
                                                       Y2= +1, -R, -R




Figure 9: Block diagram of a single-input decoder
with active "0", passive "+"

Table 7
Decoder truth table. Active signal "-"
     X          Y0           Y1          Y2
      -          -            +          +
     0           +            -          +
     +           +            +           -
                                                    Figure 11: Block diagram of a single-input
   Y0= +R, -R, +R, -L = -1, +R, +R                  decoder with active "+"
   Y1= +R, +L, -L, -L = +1, -L, -L
   Y2= +1, -R, -R, +L, +L                              Analysis of the obtained structures of single-
                                                    input decoders showed that the simpler options
                                                    are when the active signal is "-" or "+", and
                                                    passive is "0".

                                                    4. Conclusions
                                                        The analysis of the construction of multivalued
                                                    logic and its elemental base allowed us to draw the
                                                    following conclusions.
                                                        The vast majority of the implementation of
                                                    ternary elements has significant disadvantages.
                                                        These solutions either do not allow the full
                                                    implementation of ternary logic, or do not have a
                                                    general approach to its implementation, or
                                                    complicate the implementation of ternary devices
                                                    and their structure.
                                                        One of the obstacles hindering the
                                                    development of ternary technology is the lack of
Figure 10: Block diagram of a single-input          element base and a common approach to the
decoder with active "-"                             implementation of components and elements of
                                                    non-binary computers.
   The implementation of ternary devices based                 representations. Synthesis lectures on digital
on threshold logic is a way to create ternary                  circuits and systems 12. Morgan & Claypool
devices that can compete with binary in terms of               Publishers. ISBN 9781598291902.
equipment.                                               [5]   M. Ahmad, RISC-V Processor Designs
   An urgent scientific and practical task is to               Emerge,              2021,              URL:
create a general approach to the implementation                https://www.eetimes.com/risc-v-processor-
of ternary nodes and methods of synthesis of                   designs-emerge/
ternary logical and arithmetic elements, as there        [6]   S. Gottwald, A Treatise on Many-Valued
are still no standards in the development and                  Logics. Studies in Logic and Computation,
implementation of ternary elements and a single                vol. 9, Research Studies Press: Baldock,
methodological approach.                                       Hertfordshire, England, 2001.
   Thus, for the first time, the structures of           [7]   Yu. Gunchenko, L. Martynovych, K.
several variants of one-input decoder with active              Tikhonova, D. Slutsky, The concept of
signals "-", "+" and "0" based on MTEML, which                 construction of devices for ternary logic -
can be used in the construction of elements of                 Proceedings of the V All-Ukrainian
ternary computer systems, were obtained.                       scientific-practical conference Perspective
   The built devices have a much simpler                       directions of modern electronics, information
architecture compared to their counterparts.                   and computer systems (MEICS-2020)
   Analysis of the obtained structures of single-              Dnipro , November 25–27, 2020 - pp.93-94.
input decoders showed that the simpler options           [8]   Y. Gunchenko, L. Martynovych, V.
are when the active signal is "-" or "+", and                  Mezhuyev, Y. Shugailo, Y. Bercov, Design
passive is "0".                                                of a ternary RS-trigger. 2021 7th
   To build ternary computing and intelligent                  International Conference on Computer
systems, it is necessary, first of all, to develop the         Technology Applications (ICCTA 2021)
principles of a systematic approach to the                     online, held during July 13-15, 2021 in
synthesis of ternary elements and software for                 Vienna, Austria. To appear.
their interaction with each other and with existing
modern devices.
   Therefore, in further research it is expedient to
consider methods of construction and synthesis of
nodes of ternary computer systems, their
optimization, and development of principles of
mathematical modeling and software of such
systems and their elements.

5. References
[1] Multivalued       logic    //    Philosophical
    encyclopedic dictionary / VI Shinkaruk
    (editor in chief) and others. - Kyiv: Hryhoriy
    Skovoroda Institute of Philosophy of the
    National Academy of Sciences of Ukraine:
    Abris, 2002. - 742 p. - 1000 copies. - BBK
    87я2. - ISBN 966-531-128-X.
[2] Béziau J.-Y. 1997 What is many-valued logic
    ? Proceedings of the 27th International
    Symposium on Multiple-Valued Logic,
    IEEE Computer Society, Los Alamitos, pp.
    117–121.
[3] Malinowski, Gregorz, 2001, Many-Valued
    Logics, in Goble, Lou, ed., The Blackwell
    Guide to Philosophical Logic. Blackwell.
[4] D. Michael Miller; Mitchell A. Thornton
    (2008). Multiple valued logic: concepts and

</pre>