{"labels":{"en":"A Prototyping and Evaluation Framework for Research on Timing-analysable Memory Hierarchies for Embedded Multicore SoCs"},"descriptions":{"en":"scientific paper published in CEUR-WS Volume 3145"},"claims":{"P31":"Q13442814","P1433":"Q113529229","P1476":{"text":"A Prototyping and Evaluation Framework for Research on Timing-analysable Memory Hierarchies for Embedded Multicore SoCs","language":"en"},"P407":"Q1860","P953":"https://ceur-ws.org/Vol-3145/short11.pdf","P50":[],"P2093":[{"value":"Florian Haas","qualifiers":{"P1545":"1"}},{"value":"Sebastian Altmeyer","qualifiers":{"P1545":"2"}}]}}