This paper introduced possible ways to improve the MOSFET performance from the perspective of structure and material. The two updated MOSFET models fin field-effect transistor (FinFET) and gate-all-around field-effect transistor (GAAFET) are used to derive the conclusion in this word. To improve structure-based performance, results from simulations show short channel effect and self-heating effects are to be minimized. Strain engineering is studied with material analysis. This paper concluded that performance of FET can be improved by improving the mobility of electrons or holes by changing crystal lattice structure from the perspective of strain engineering. Other than that, changing structure to minimize short channel effect, making channels more spherical shape, and minimizing the thermal resistance and thermal capacitance are proved to be the solutions to improve performance of FET in this paper.
To show the structural modification in FETs, we first compare the contact area between gate and channel of planer FET, FinFET, and GAAFET. In Planar FET, there’s only one interface which is the bottom of the gate. In FinFET, the contact area between gate and channel is largely increased: there are three interfaces between channel and gate as shown in fig 1.
In GAAFET, the channel is surrounded by the gate (as shown in fig 2) which means there are four interfaces between the gate and channel. That’s why it is called gate-all-around FET. It looks like the fin on FinFET is cut horizontally into several nanowires which forms the channel of GAAFET. As a result, the contacting area of GAAFET is even greater than FinFET.
The ranking of the contact area between channel and gate is: GAAFET > FinFET > Planar FET.
The ranking of control of gate over channel also follows this sequence because larger contacting area between channel and gate means greater control of gate over channel. GAAFET has greatest contacting area between gate and channel which means GAAFET’s gate has better control over channel. Compared to GAAFET, FinFET encounters barriers in further limiting short channel effect. In FinFET, the prevalent method is to reduce fin width which can enhance the control of the gate[4].However, too thin fin width will cause scattering, resulting in reduction of the density of available states in the band edge, which means carriers would need more energy to occupy states in the conductive band[4]. Modifying its structure by moving to GAAFET is a reliable solution. In general, GAAFET has better structure to overcome short channel effect[5].
In GAAFET, the short channel effect is better controlled which results in better control over draininduced barrier lowering(DIBL). DIBL means applying drain bias to lower the energy barrier between source and channel so electrons can easily flow into the channel. DIBL will reduce the difference between "on" and "off" states. Better control of DIBL enables higher drive current with leakage current unchanged[1]. Since delay is given by CV/I(capacitance*voltage/current), with higher drive current, the switching speed is faster[1]. The working voltage of FET is also lowered due to better subthreshold swing and better control of DIBL[1]. However, the series resistance in GAAFET is greater, the drive current is reduced which means drive current in GAAFET is comparable to drive current in FinFET[1].
The table below shows performance of FinFET and GAAFET:
Ion (µA) 41.60
According to the Figure 3, delay of GAAFET is lower and drive current is greater when effective channel length is less than 16nm. GAAFET is better at lower effective channel length.
To further improve the performance of GAAFET, corner effects should be addressed. Corner effect has more influence on performance of GAAFET than that of FinFET.[6] To avoid corner effects, channels can be made into a more spherical shape.[5] The electric field is distributed more evenly in the spheric nanowire as shown in fig 4.
For a channel with diameter of 7 nanometers with a 2-nanometer-thick oxide layer, the subthreshold leakage current in the cylindrical channel is 1/5 time of the square shaped channel.[5]
Apart from avoiding channel effect, there are other structural considerations. For example, is nanosheet FET better than nanowire FET since it has greater sectional area which lowers series resistance? Does nanosheet FET have lower parasitic capacitance than nanowire ones? These are directions for future research in the shape of GAAFET.
When electric current passes through a transistor, the kinetic energy of flowing electrons in a semiconductor is converted to thermal energy, heat. The self-heating effect defines such unwanted heat in the system. In general, the electrical conductivity decreases as temperature rises exponentially in semiconductors. The rise of thermal energy cases disabled the function of transistors, also sharply shortening the lifespan of transistors. Therefore, researchers are devoted to minimizing the self-heating effect or at least reducing the self-heating effect in an acceptable range.
Shortening the channel region is required to minimize the self-heating effect. Examined by Chuntaek Park and Ilgu Yun by applying different channel lengths to GaaFET under 5 GHz frequency, Fig 5 shows that the normalized thermal time constant ( τ TH ) increases with channel width. The thermal time constant is defined as the product of thermal resistance (R TH ) and thermal capacitance (C TH). From the graph, normalized thermal resistance has a clear pattern to decrease with channel width while normalized thermal capacitance decreases with channel width. As a result of such two opposite characteristics, to minimize the self-heating effect is to look for the max product of thermal resistance and thermal capacitance.
However, shortening the channel can potentially lead to a short channel effect. Therefore, it is important to find a balance between the limiting heat effect and the short channel effect.
This part will have a brief review of the modern FinFET(Fin-shaped Field Effect Transistor) fabrication process and the strained structure in FinFET. Through integrated process optimization [8,9] and interfacial layer engineering [10], the performance advantages of SiGe channel on Si-pFETS can be realized. And how does the strain make the crystal lattice displace is shown in figure 6. Strain engineering can improve the performance of FinFET devices by applying stress to improve mobility (reduce effective mass and reduce scattering) = ∗ (1)
The process of fabrication are mentioned on the figure 7 and 8 before respectively. And the related manufacturing processes are dope, deposition, lithography, implantation, planarization and etching. The fabrication of modern FinFET is very complicate, and the parameter of each step is also in a dominant position for getting an ideal performance of transistors and the excellent performance of IC.
Stress/Strain technique is one of the promising techniques among many technologies for FinFETs with different piezo materials and high-k/metal gates. Recently, the dual strain Si/SiGe channel FinFET fabricated on the strain relaxation buffer (SRB) layer, it includes tensile strain Si-nFET and compression strain SiGe-pFET, have been proven to enhance electrons and holes mobility under the node of 7nm technology [11]. Two strained structures have been proved for the improvement of FinFET.
The first strained silicon structure applied to FinFET is Si on SiGe SRB (stress relaxed buffer), as shown in figure 9 [12]. The structure is a FinFET with SRB under the fin-shaped channel, and SiGe SRB could apply stress to the channel to make the device work more excellent. However, because of the difficulty of decoupling the strain in the channel, it is not completely explored for the contribution of the channel strain to the mobility of holes and electrons.
The second structure is shown in figure 10. It is a FinFET with SiGe S/D epitaxy. The material of the source epitaxy layer and drain epitaxy layer is SiGe. And also the fraction of Ge content in SiGe determines the improvement for device performance. It has been verified in some research these days [13].
In conclusion, both SRB and S/D epitaxy layers can boost the performance of modern FinFET. In the next part, the discussion is about the quantitative representation of device performance improvement.
In this section, I will discuss the performance optimization of the strain engineering finfet
The research and simulation is based on a FinFET with both S/D epitaxy and SiGe SRB(stress relaxed buffer). And the parameters are shown below, the structure of the strained FinFET is also shown in fig 11. This FinFET is fabricated on Si substrate and it has Si0.9Ge0.1 SRB under the fin, and also with Source and Drain epitaxy layer surrounded. They have simulated the 3D displacement profile (amount of strain) for different Ge content and obtained the optimum result at Ge mole fraction of 0.3 because of high mobility.
According to their simulation. The electrical parameters are shown in Table 2. When the content of Ge is 0%, in linear region at =50mV, =213.389mV, =0.0145nA, =20.9μA, SS=71.214mV/dec, in saturation region at =0.7V, =199.214mV, =0.0269nA, =0.0568μA, SS=70.536mV/dec.
When the content of Ge is 10%, in linear region at =50mV, =178.15mV, Ioff=0.0436nA, =50.9μA, SS=63.935mV/dec, in saturation region at =0.7V, _ = 165.201 , =0.0849nA,
=152μA, SS=66.214mV/dec.
When the content of Ge is 30%, in linear region at =50mV, =155.761mV, =91.7μA, SS=65.325mV/dec, in saturation region at =0.7V, =131.445mV, =0.159nA, =0.299nA, =258μA, SS=66.214mV/dec.
By changing the Ge% in fin SRB, the electrical parameters of the above-mentioned devices, such as , ,
, subthreshold slope (SS), and DIBL, are calculated. It is found that the key equipment parameters (such as SS and DIBL) of all equipment are consistent, which is closer to ITRS requirements. With a germanium content of 30%, the device showed relatively best results, and the high turn-off current found was affected due to the high turn-on current and other standardized parameter values. As the band gap of the S/D region decreases, DIBL decreases with the increase of Ge content, so the mobility increases, which leads to the decrease of DIBL. The extracted DIBL of different germanium content (such as 0%, 10% and 30%) were 25.94, 23.28 and 23.56 mV/V, respectively.
Toward extreme scaling of field-effect transistors, by modifying the structure and using strain material, FET performance can be improved by those two methods. GAAFET is a structure that has better control in SCE and DIBL than FinFET while more subject to self-heating effects. And strain material can improve the mobility of electrons or holes by applying force on crystal lattice which can also make FET performance better.
MAY 2017
VOL. 58, NO. 6, JUNE 2011 [1] Huang, Y., Chiang, M., Wang, S. & Fossum,G., “GAAFET Versus Pragmatic FinFET at the 5nm
Si-Based CMOS Technology Node”, Journal of the Electron device society, Volume 5, NO. 3, [2] Conzatti, F., et al. “Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations”, IEEE TRANSACTIONS ON ELECTRON DEVICES, NO. 6, Issue NO. 07, July 2017
State Device Research, 2003 [3] Cutress, I., “Samsung Announces 3nm GAA MBCFET PDK, Version 0.1”, retrieved from
Samsung Announces 3nm GAA MBCFET PDK, Version 0.1 (anandtech.com) [4] Bhole, M., Kurude, A. & Pawar, S., “FinFET- Benefits, Drawbacks and Challenges”, International
Journal of Engineering Sciences & Research Technology, Bhole, 2(11): November, 2013 [5] Mohan, C., Choudhary, S., Prasad, B., Gate All Around FET: “An Alternative of FinFET for Future
Technology Nodes”, International Journal of Advance Research in Science and Engineering, VOL. [6] Burenkov, A. & Lorenz, J., “Corner effect in double and triple gate FinFETs”, European Solid[7] C. Park and I. Yun, "Degradation of Off-Phase Leakage Current of FinFETs and Gate-All-Around FETs Induced by the Self-Heating Effect in the High-Frequency Operation Regime," in IEEE Transactions on
Nanotechnology, vol.
19, pp.
308-314, 2020, doi: 10.1109/TNANO.2020.2986540. [8] Guo, D., et al. "FINFET technology featuring high mobility SiGe channel for 10nm and beyond." 2016 IEEE Symposium on VLSI Technology. IEEE, 2016. [9] Hashemi, P., et al. "Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT∼ 7Å and scaled dimensions down to sub-4nm fin widths." 2016 IEEE Symposium on VLSI Technology. IEEE, 2016 [10] Tsutsui, Gen, et al. "Technology viable DC performance elements for Si/SiGe channel CMOS
FinFTT." 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016. [11] Xie, R., et al. "A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels." 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016. [12] Lee, C. H., et al. "A comparative study of strain and Ge content in Si 1− x Ge x channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs." 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017. [13] Dash, T. P., et al. "Stress-induced variability studies in tri-gate FinFETs with source/drain stressor at 7 nm technology nodes." Journal of Electronic Materials 48.8 (2019): 5348-5362. [14] Jena, J., et al. "Performance Analysis of FinFETs with Strained-Si Fin on Strain-Relaxed Buffer." 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS). IEEE, 2020. [15] T. P. Dash, J. Jena, E. Mohapatra, S. Dey, S. Das, and C. K. Maiti, “Role of stress/Strain Mapping in Advanced CMOS Process Technology Nodes,” in IEEE DevIC, pp. 21-25, 2019. [16] S.E. Thompson et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Tans.
Electron Devices, vol. 51, pp. 1790-1797, Nov.2004. [17] T. P. Dash, S Dey, S. Das, E. Mohapatra, J. Jena, C. K. Maiti, “Strain Engineering in nanowire field-effect transistors at 3 nm technology node”, in Physica E: Low-dimensional Systems and Nanostructures, vol. 118, pp. 113964, 2020.