Design of a Software Defined Radio Using Soc Builder

Abstract

This paper deals with the development of SDR systems on XILINX RF-SOC devices using the MATHWORKS "SOC Builder" tool. RF-SOC are complex devices integrating microprocessors, FPGA, and RF converters (both ADC and DAC). This complexity requires engineers' transversal competence sweeping from software, hardware, and RTL coding capabilities. For this reason, although these devices are very powerful, the implementation of complex systems on them is very demanding work. The MATHWORKS SOC builder tool is a promising toolchain that allows designers to develop complex SDR systems on XILINX RF-SOC using the Simulink environment, without the necessity to write c/c++ code and without the knowledge of HDL language. This work analyzes this interesting environment underlining its potential in the development of SDR systems. Experimental results are presented in terms of hardware complexity, maximum frequency and power consumption.

1. Introduction

of algorithms the use of FPGA is alwaysmore a necessity.

FPGA allows to realize customizable datapaths characterIn the last few years, the introduction of RF Analog ized by high computation capabilities, reconfigurability to Digital Converters and Digital to Analog Convert- and reduced power consumption. These feature are very ers made possible the development of Software Defined important for the realization so new generation comRadio (SDR) characterized by an always more reduced munication systems that integrates advanced DSP and number of analog components,[ 1, 2 ]. SDR introduce sev- machine learning requirement[ 15, 16, 17, 18, 19 ]. XILeral advantages as the ability to receive and transmit INX RF-SOCs ofer these interesting feature integrating various modulation schemes, the ability to upgrade func- in the same chip also high speed Analog to digital contionalities downloading and running new firmware, the verters and Digital to analog converters. In a single chip possibility of adaptively choosing operating frequencies designer have all the devices necessary to implement and the reduction of analog hardware. For all those rea- complex software defined systems for what concerns sons, in the last few years, electronic devices manufactur- the digital parts and the converters. Although RFSOCS ers proposed new microchips with RF ADC and RF DAC are very interesting objects their use requires transvercapabilities. Among these devices, XILINX RF-SOCS are sal knowledge sweeping from RTL design, to software very interesting because they integrate into a single chip design. The MATHWORKS SOC BUILDER tools is a a microprocessor, an FPGA, and several RF ADC/DAC very interesting design flow that allows the designer to [3, 4? ]. The possibility to have all these elements in a configure RFADC/DAC, program microprocessor, and desingle chip is very interesting for several reasons: the sign FPGA systems directly in the MATLAB/SIMULINK PCB design process is considerably simplified; modern environment without the necessity to write c/c++ code communication systems are very complex integrating and without the necessity to know HDL languages like several functionalities such as communication algorithms VHDL, Verilog/System Verilog. In this paper, we explore [ 5, 6, 7, 8 ], machine learning [ 9, 10, 11, 12, 13 ], etc. that the SOC Builder tool capabilities. To do it we realized an require diferent processing devices. In this scenario, the SDR transmitter possibility of partitioning the processing between the microprocessor and FPGA is a very important aspect. The microprocessor can be used to manage peripherals and 2. The XILINX RF-SOC implement low throughput algorithms while FPGA can be used for custom datapaths [ 14 ]. For modern communication systems characterized by heterogeneity in terms Xilinx Zynq Ultrascale+ RFSoC integrate programmable logic,n ARM cortex system and RF ADC/DAC in the same SoC.

The integration of these components in a single die allows to save area and power and simplifies the design of the board being the RF signal is directly sampled withof all the harware complexity and the design.

XILINX RFSoC devices allow to directly sample RF signals until 6 GHz. This aspect make these devices suitable for applications using bands L, S and C as for example: • Multi-band 5G networks • Massive MIMO • Phased Array systems • Space communications • RADAR

The block diagram of the XILINX RFSoC is shown in

Figure ??.

The RFSoC Analog-to-digital and Digital-to-analog converters,ofer the possibility to manage real and complex signals (I/Q). The structure of ADCs is organized in tiles. Each tile is composed of 4 ADCs and 1 PLL with 12 or 14 bits operation mode. DAC are organized with 4 14 bits DACs and 1 PLL with a bandwidth of 4 GHz and output frequency until 5 GHz. The device is 40x40-mm in size, with a 1517-pin ball grid array (BGA) package and is manufactured with a 16-nm Fin field-efect transistor (FinFET) process [ 2 ]

3. SDR design with SOC builder

In order to simplify the design, the SOC Builder tool ofers a script called SocModelCreator that can be used to generate reference designs of diferent tipology. The script launches a GUI that allows designers to set many parameters. Among these parameters the most important are: • The possibility to choose among several reference design. • The possibility to set ADC and DAC directly in matlab without the necessity of other tools • The possibility to include in the project external I/O interfaces as for example the switched the LEDs. • The possibility to include AXI register to read and write data from Simulink to the board • The possibility to choose to realize a project for the ARM+ the FPGA or FPGA only • The possibility to manage external DDR4 memory.

In Fig.?? is shown the Graphical User Interface for the

SOC configuration ad system developement.

The most interesting feature is surely the possibility to set the ADCs and the DACs. Modern converters are in general very complex devices and their configuration is a very dificult operation. SocModelCreator allows conifguring these devices using this simple GUI simplifying the configuration process.

There is the possibility to set sample frequencies and other parameters. For example, converters can operate in real mode or in complex IQ mode. In the case of IQ modes, it is also possible to configure mixers for the up and the down-conversion of the signal. In fact, XILINX RF-SOC has integrated mixers that allow the designer to perform up and down conversion without the necessity to waste FPGA hardware resources.

In addition to the mixers, XILINX RF-SOC provide also hardware interpolators and decimators in the proximity of DAC and ADC. The presence of these blocks simpliifes the design. Another interesting feature regards the possibility to interface the converters in frame-based mode. In other words, it is possible to send and receive data through converters using more than one sample per clock cycle. This feature allows designers to create parallel datapaths characterized by a reduced clock frequency [ 20 ],[ 21 ]. For example, let’s consider setting 4 samples for clock cycles. If the sample rate of the converters is set for example to 1 GHz, the possibility to have 4 samples for the clock cycle makes it possible to split the datapath into 4 parallel datapath having a data rate of 250 MHz. In this way, it is easier to not violate the clock constraint during the STA phase.

The SocModelCreator tool, one configured for a reference design, create a Simulink model like the one shown in Fig?? This model is divided into two main part, a block for the FPGA and a block for the microprocessor. Diferent from the traditional SOC development environment where design has to use HDL languages to program the FPGA and C/C++ to program the microprocessor, using SOC builder designer has to use only Simulink with a consequent simplification of the flow design. Both the FPGA and microprocessor algorithm have to be described in terms of block diagram using Simulink

4. Experimental results

In order to evaluate the potential ofered by SOC builder in the design of SDR systems we realize a QPSK modulator composed of a bit generator, a squared raised cosine iflter with interpolation, and a DDS. We use the DDS for the operation of upconversion.

After the design of the Simulink block diagram, the system has been synthetized and implemented directly in the MATLAB environment. This is possible because the MATLAB callS, configure, and execute the XILINX VIVADO tool. In this way, designers can complete the design flow directly in MATLAB without the necessity to manually use VIVADO and other complex tools. In case of synthesis failure or STA violation the SOC BUILDER tool adverts the design with alerts in the TCL.

The use of SOC builder speeds up the design process making possible the realization of SDR systems in a very reduced time if compared with traditional design flows.

Advanced synthesis instruction allows designer to set important parameters directly in Simulink without the necessity to do it in VIVADO. For example, it is possible to manage the re-timing register in order to improve the performance in terms of throughput.

The implemented system has been tested using the XILINX ZCU111 board shown in Fig. ??

Implementation results underline a power consumption of about 8W, a maximum clock frequency of 100 MHz and a very reduced use of the hardware resources of the FPGA. The entire modulator has been realized using only: • 14,531 LUT • 19,233 Flip Flop • 26 DSP • 13 BRAM

The entire modulator has been developed maintaining 16-bit of accuracy in all the data path.

5. Conclusions

In this paper, we explored the capabilities of a new MATHWORKS tool called SOCBUILDER for the design of SDR based on XILINX RF-SOC devices.

A Q-PSK modulator has been realized and implemented on a XILINX ZCU111 board. The entire system has been designed entirely in Simulink without the necessity to use other software tools. SOCBUILDER allows the possibility to perform fixed-point analysis, simulations, and customization in the synthesis providing the possibility to manage hardware primitives and synthesis settings as the retiming. The possibility to simulate the DUT (Design Under Test) in the Simulink environment in addition to the other Simulink toolbox help designer in the verification stage of the design. DUT can be stimulated directly with real case data. Implementation results show that SOCBUILDER allows to implement communication system with reduced hardware complexity.

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