=Paper= {{Paper |id=Vol-3398/p12 |storemode=property |title=Multi-Valued Logic Digital Circuits for Realizing a Complete Computer Architecture |pdfUrl=https://ceur-ws.org/Vol-3398/p12.pdf |volume=Vol-3398 |authors=Alessandro Simonetta,Maria Cristina Paoletti,Alessio Venticinque |dblpUrl=https://dblp.org/rec/conf/icyrime/SimonettaPV22 }} ==Multi-Valued Logic Digital Circuits for Realizing a Complete Computer Architecture== https://ceur-ws.org/Vol-3398/p12.pdf

Multi-Valued Logic Digital Circuits for Realizing a
Complete Computer Architecture
Alessandro Simonetta1 , Maria Cristina Paoletti1 and Alessio Venticinque2
1
Department of Enterprise Engineering, University of Rome Tor Vergata, Rome, Italy
2
Department of Electrical and Information Engineering, University of Naples Federico II, Napoli, Italy

Abstract
The objective of this paper is to lay the foundation for the construction of a computer architecture using entirely multivalue
logic (MVL). To achieve this ambitious result, it is necessary to know how to design all the digital components that normally
form the basis of a computer’s operation. These are combinational circuits dedicated to mathematical computation and
sequential circuits in charge of storing information. In the paper, a general methodology is proposed that can be used for
the construction of digital circuits capable of working independently of the basis of representation of multivalue logic and
the physical quantity used for encoding logical states.

Keywords
MVL, Multi-valued logic, CPU, Computer architecture, digital circuit, adder look ahead

1. Introduction
𝑝
The subject of multivalue logic as a natural evolution of 𝑛∑︁−1 𝑝−1
∏︁
representation in the binary system is a much debated 𝑓 (𝑥 𝑜 , 𝑥 1 , ..., 𝑥𝑝−1 ) = 𝑘 𝑖 · 𝑆𝑐𝑗 (𝑖)(𝑥𝑗 ) (2)
issue [1], [2]. Although various solutions, including tech- 𝑖=0 𝑗=0

nological ones, have been proposed, but at present there where:
is no calculator capable of operating in multivalued logic
[3], [4], [5]. However, with the arrival of memresistors [6] • 𝑘𝑖 is the value taken at the i-th position in the
and a multiplicity of multi-state semiconductor compo- combination, with 𝑘𝑖 ∈ T;
nents, the scenario is evolving and the theory developed • 𝑐𝑗(𝑖) is the j-th digit of the number 𝑖, represented
in [7] could find easy application. The theory we are in base 𝑛 with 𝑗 ∈ {0, ..., 𝑝 − 1};
going to describe is based on the extension of Boolean • 𝑆𝑐𝑗 (𝑖) is the value selector 𝑐𝑗 (𝑖) applied to
algebra and the binary numbering system toward an operand 𝑥𝑗 with 𝑗 ∈ {0, ..., 𝑝 − 1} e 𝑖 ∈
𝑛-valued (discrete) numbering system [8], [9]. In this {0, ..., 𝑛𝑝 − 1};
paper we will start from the theoretical definition and
gradually go on to realize all the digital components that Thus, to express any MVL function 𝑓 , p+2 basis function
characterize a traditional computer architecture. are sufficient: 𝑝 selection, addition and multiplication
functions.

2. Method 2.1. The selection functions
The proposed method use the teory in [10]. Assum- The selection functions 𝑆𝑖 with 𝑖 ∈ {0, ..., 𝑛−1}, that we
ing that we have a domain of discrete values T = can call Selectors too, are unary functions. We can define
{0, 1, .., 𝑛 − 1}, we can easily show that any function 𝑓 : as many selectors as there are symbols in the domain T.

𝑓 : T × ... × T → T (1) 𝑆𝑖 : T → B (3)
can be expressed as a linear combination of the input A selector is able to check whether the value of the
variables: operand matches a value in the set T:
{︃
ICYRIME 2022: International Conference of Yearly Reports on Infor- 1 𝑠𝑒 𝑡 = 𝑖
matics, Mathematics, and Engineering. Catania, August 26-29, 2022 𝑆𝑖 (𝑡) = (4)
" alessandro.simonetta@gmail.com (A. Simonetta); 0 𝑠𝑒 𝑡 ̸= 𝑖
mariacristina.paoletti@gmail.com (M. C. Paoletti)
0000-0003-2002-9815 (A. Simonetta); 0000-0001-6850-1184 with 𝑖, 𝑡 ∈ {0, ..., 𝑛 − 1}. Using the selection functions,
(M. C. Paoletti); 0000-0003-3286-3137 (A. Venticinque) any combination of the input variables can be identified.
© 2022 Copyright for this paper by its authors. Use permitted under Creative Commons License
Attribution 4.0 International (CC BY 4.0). For example, to check if all variables 𝑥0 , ..., 𝑥𝑝−1 have
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Workshop
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http://ceur-ws.org
ISSN 1613-0073
CEUR Workshop Proceedings (CEUR-WS.org)

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Alessandro Simonetta et al. CEUR Workshop Proceedings 78–89

the value 𝑛 − 1 except 𝑥0 which must be equal to 1, we 3. MVL digital circuits
can use the following function:
In this section, we will see how it is possible to construct
all the circuits that form the basis of a traditional com-
𝜑 = 𝑆1 (𝑥0 ) · 𝑆𝑝−1 (𝑥1 ) · ... · 𝑆𝑝−1 (𝑥𝑝−1 ) (5) puter architecture [11], [12]. Thus, we will start with
combinational circuits, those in which the output is a
which returns the value 1 exclusively in the case where function of the inputs, and then we will consider the
the input variables meet the requirement: smallest memory element, the D Latch. To accomplish
this task we will use the same architectural choice made
(𝑥0 , ..., 𝑥𝑝−1 ) = (1, 𝑛 − 1, ..., 𝑛 − 1) (6) in [10], and supported by studies in [13], thus a logic
based on 4 values that coincides with the base-4 num-
2.2. Sum bering system. The four logic values will be represented
through the voltage levels as reported in table 1.
Let us consider the summation of equation 2, we observe
that only one term in the summation will be valued at 𝑘𝑤
corresponding to the coding in base 𝑛 of 𝑤. Indeed, all Table 1
the terms of the summation are null except the one corre- MVL levels
sponding to the combination identified by the selection Interval
Logic level 𝑉𝑖𝑑𝑒𝑎𝑙
functions: 𝑉𝑚𝑖𝑛 ≥ 𝑉𝑚𝑎𝑥 <
𝑓 (𝑥𝑜 , 𝑥1 , ..., 𝑥𝑝−1 ) = 𝑘𝑤 (7) 𝐿0 0 1.25 0.625
𝐿1 1.25 2.50 1.875
2.3. Multiplication 𝐿2 2.50 3.75 3.125
𝐿3 2.50 5.00 4.375
With reference to the generic term of the summation of
the equation 2, it can be expressed by a function 𝜑: We also studied the behavior of the proposed circuits
by verifying the limits of the adopted components [14],
𝜑 : T × B × ... × B → T (8)
[15], [16]. In particular, the details for the configuration
that is equivalent to 𝜃: of the components are the following:

𝜃 :T×B→B (9) • AND and OR logic gates:
– Td = 10n
thus: – Ref = 0.5
– Trise = 5n
𝑡 · 𝑏0 · 𝑏1 · ... · 𝑏𝑝−1 = 𝑡 · (𝑏0 · 𝑏1 · ... · 𝑏𝑝−1 ) = 𝑡 · 𝑏 (10)
– Tfall = 5n
Indeed, it is sufficient to make a function with two – Vhigh = 5
operands: one MVL and the other binary. This function • inverted gates:
returns as output the value of the multivalue input (if
– Td = 5n
the binary value is unity) or zero in the other case:
– Ref = 0.5
– Trise = 5n
{︃
0 𝑠𝑒 𝑏 = 0
𝜃(𝑏, 𝑡) = (11) – Tfall = 5n
𝑡 𝑠𝑒 𝑏 = 1
– Vhigh = 5
with 𝑡 ∈ T and 𝑏 ∈ B.
Recalling that the logical conjunction operation returns
a result that is equivalent to multiplication between bits
3.1. LTSpice
(the result is one if and only if all the operands are 1), we The electronic circuits that we will describe, were de-
can conclude that it is possible to use the AND operator signed and validated using the product LTspice® XVII by
to compute the value 𝑏 in the binary domain. At this Analog Device Corporation [17], distributed on the devel-
point it is possible to use that bit to calculate the MVL oper’s website. This simulator has a graphical interface
function 𝜃(𝑏, 𝑡). Without loss of generality and with the to build the schematics and allows the user to test the
purpose of making the paper easier to read, we will use circuits. The tool also allows new features to be defined
the symbol normally used for multiplication to denote the and imported as elements in the various schemes. There-
function 𝜃 conscious of the fact that it is multiplication fore, we chose to reuse the circuit diagrams proposed in
between values pertaining to different domains (B ⊆ T). [10] regarding the selectors, multiplexer and half-adder
to design new ones.

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3.2. Combinational Circuits

Table 2
MVL true table: adding single MVL digits

𝐴𝑖 𝐵𝑖 𝐶𝑖 𝑆𝑖 𝐶𝑖+1 𝑔𝑖 𝑝𝑖
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 1 0 0 0
0 1 1 2 0 0 0
0 2 0 2 0 0 0
0 2 1 3 0 0 0
0 3 0 3 0 0 0
0 3 1 0 1 0 1
1 0 0 1 0 0 0 Figure 1: Look-ahead full adder single digit detail
1 0 1 2 0 0 0
1 1 0 2 0 0 0
1 1 1 3 0 0 0
1 2 0 3 0 0 0
1 2 1 0 1 0 1
1 3 0 0 1 1 0
1 3 1 1 1 1 0
2 0 0 2 0 0 0
2 0 1 3 0 0 0
2 1 0 3 0 0 0
2 1 1 0 1 0 1
2 2 0 0 1 1 0
2 2 1 1 1 1 0
2 3 0 1 1 1 0
2 3 1 2 1 1 0
3 0 0 3 0 0 0
3 0 1 0 1 0 1
3 1 0 0 1 1 0
3 1 1 1 1 1 0
3 2 0 1 1 1 0
3 2 1 2 1 1 0
3 3 0 2 1 1 0
3 3 1 3 1 1 0
with 𝐴𝑖 , 𝐵𝑖 , 𝑆𝑖 ∈ T and 𝐶𝑖 , 𝐶𝑖+1 , 𝑔𝑖 , 𝑝𝑖 ∈ B

MVL look-ahead adder In this section we will study
the behavior of the circuit MVL look-ahead adder of 4- Figure 2: Look-ahead full adder blocks scheme
digit base-4 words. In [7] a half-adder consisting of two
inputs and two outputs in base 4 has already been pre-
sented, and starting from this circuit the authors design as indicated in table 3.
a full-adder in [10]. The most obvious problem with this
circuit is the response time, which depends on the prop-
Table 3
agation delay of the carryover in the various half-adders. Adding two MVL words of 𝑞 length
The time grows as the number of digits of operands and
thus half-adders used to construct the adder increases 𝐶𝑞 𝐶𝑞−1 ... 𝐶0
𝐴𝑞−1 ... 𝐴0 +
[18], [19]. Indeed, in a look-ahead adder the carryover
𝐵𝑞−1 ... 𝐵0 =
is not affected by the delay of circuit elements placed
in cascade. Consider two MVL words of length 𝑞: 𝑆𝑞 𝑆𝑞−1 ... 𝑆0
𝐴 = {𝐴𝑞−1 , ..., 𝐴0 } and 𝐵 = {𝐵𝑞−1 , ..., 𝐵0 }, if the
calculated carryovers are 𝐶 = {𝐶𝑞 , ..., 𝐶1 } and 𝐶0 is If by the variables 𝑝𝑖 and 𝑔𝑖 we denote the generated
the potential carryover of a previous least significant and propagated carryover, respectively, we can build the
word, we can calculate the sum word 𝑆 = {𝑆𝑞 , ..., 𝑆0 } truth table (table 2) related to the sum of two generic

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Figure 3: Look-ahead adder with 4 MVL digits

MVL digits. The values of 𝑝𝑖 and 𝑔𝑖 are given by the a switch driven by a binary signal, can send the value
relation 12 for a cirucite in which the signals are in basecorresponding to 𝐿1 to the second half-adder. The adder
n. circuit will use two half-adders to calculate 𝑆𝑖 = 𝐶𝑖 +
{︃ 𝐴𝑖 + 𝐵𝑖 ; the variable 𝑔𝑖 will be calculated from the first
0 𝑖𝑓 𝐴𝑖 + 𝐵𝑖 ≤ 𝑛 − 1 half-adder while 𝑝𝑖 will be calculated using the selection
𝑔𝑖 = (12)
1 𝑖𝑓 𝐴𝑖 + 𝐵𝑖 > 𝑛 − 1 function to understand whether 𝐴𝑖 + 𝐵𝑖 = 𝑛 − 1 (figure
{︃ 1). This component will be replicated for each couple of
0 𝑖𝑓 𝐴𝑖 + 𝐵𝑖 = 𝑛 − 1 input in order to build a look-ahead adder as in figure
𝑝𝑖 = (13)
2. In figure 3 a look-ahead adder circuit with 4 MVL
1 𝑖𝑓 𝐴𝑖 + 𝐵𝑖 ̸= 𝑛 − 1
digits is made. This circuit can be used to perform MLV
In the same way, in the case of the MVL, we can determine word sum with lengths multiple of 4: for example, we can
in advance the values of the carryovers 𝐶 ∑︀𝑖+1 from
∏︀ the add up 8 MVL digits by cascading two circuits (figure 4).
variables 𝑔𝑖 and 𝑝𝑖 . Using the symbols and , for The behavior of the circuit is verified through a concrete
logical disjunction (OR) and logical conjunction (AND), example: suppose we add the value 𝐴 = 310200023
respectively, we can write the equation 14. with 𝐵 = 33212131 and that the carryover 𝐶0 will be 0.
The expected result is the number S=130232220 as can
𝑖 𝑖−1 𝑖
∏︁ ∑︁ ∏︁ be easily seen from the calculation shown in the table 4.
𝐶𝑖+1 = 𝑔𝑖 + 𝐶0 𝑝𝑗 + 𝑔𝑘 𝑝𝑗 (14)
𝑗=0 𝑘=0 𝑗=𝑘+1
Decoder A decoder is a combinational circuit with 𝑟
However, the values of the carryovers (𝐶𝑖+1 ), determined inputs and 𝑛𝑟 outputs. It returns as output the decoded
in such a way, are in the binary domain, instead we need form of a coded word given as input.
the value corresponding to the logical level 𝐿1 of the table Starting with the most basic decoder, which decodes a
1. Then a transduction element is needed that, through single digit in the four possible values, we will construct

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Figure 4: Look-ahead adder with 8 MVL digits

Table 4 Table 5
An example of two words sum of 8 MVL digits MVL True Table
1 1 1 1 𝐼𝑁 𝑆0 𝑆1 𝑆2 𝑆3
3 1 0 2 0 0 2 3 +
3 3 2 1 2 1 3 1 = 𝐿0 𝐿1 𝐿0 𝐿0 𝐿0
𝐿1 𝐿0 𝐿1 𝐿0 𝐿0
1 3 0 2 3 2 2 2 0 𝐿2 𝐿0 𝐿0 𝐿1 𝐿0
𝐿3 𝐿0 𝐿0 𝐿0 𝐿1

the decoder that decodes two-digit words. Making a
single-digit decoder is a simple task because it is sufficient Since we have two one-value decoders, it is possible to
to use the selection functions by applying them to the construct a decoder with 𝑟 = 2 and 42 = 16 outputs (fig-
same input (figure 5). ure 6) using an AND gates array that realizes all possible
combinations of pairs relative to the outputs of the two
decoders. The figure 6 shows the circuit with the compo-
nents X2 and X3 representing single-digit decoders. In
this case, if the input is the number 134 (𝐼𝑁1 = 𝐿1 and
𝐼𝑁0 = 𝐿3 ) the only enabled digit in output would be
𝑂7 (logic level 𝐿1 ) .
Figure 5: MVL Decoder 1x4

Encoder The encoder is a combinational circuit too,
{︃ that receives as input 𝑛𝑟 MVL digits and returns as output
𝐿1 𝑖𝑓 𝐼𝑁 = 𝑖 𝑟 MVL digits. It performs the opposite function to the
𝑆𝑖 (𝐼𝑁 ) = (15)
𝐿0 𝑖𝑓 𝐼𝑁 ̸= 𝑖 decoder: it receives a decoded representation as input
and provides the corresponding encoding as output. The
Based on the value of the input IN, it will select the cor- figure 14 shows an encoder with 16 inputs and 2 outputs.
responding output (level 𝐿1 ), while all other outputs will Each 𝐼𝑁𝑖 input passes through a 𝑆𝑖 switch that detects
be zero (level 𝐿0 ), according to what reported in table 5. the 𝐿1 level at the input (equation 16).

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Figure 6: MVL Decoder 2x16

{︃ the corresponding switch by propagating the IN signal
𝐿1 𝑖𝑓 𝐼𝑁𝑖 = 𝐿1 to the output 𝑂𝑈 𝑇3 .
𝑆1 (𝐼𝑁𝑖 ) = (16)
𝐿0 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
Shifter In this section we will look exclusively at
To make the circuit simpler, we grouped the selector parallel-type shifters, which are normally used to per-
switch outputs that would determine the same value on form mathematical operations (e.g. multiplication and
the output signals 𝑂𝑈 𝑇 1 and 𝑂𝑈 𝑇 2. Note that the division by base). In general, having a summation and a
output of each enabled switch causes its closure, which shifter makes it possible to perform multiplication and
brings the output level value. For example, if 𝐼𝑁 7 = 𝐿1 division operations for general numbers as long as they
the output of selector 𝑆𝐸𝐿8 enables the OR gates that are expressed in terms of the base [20]. An example
determine 𝑂𝑈 𝑇 1 = 𝐿1 and 𝑂𝑈 𝑇 0 = 𝐿3 . of multiplication between 17 and a generic number 𝑥,
with 𝑥 ∈ N, performed through the use of shifting and
Demultiplexer The demultiplexer (or simply demux) addition, is given in the equation 18.
is a circuit typically used to restore multiplexing pro-
duced by a multiplexer in communications. Its treatment 17 · 𝑥 = (41 + 40 ) · 𝑥 = 41 · 𝑥 + 40 · 𝑥 (18)
in MVL can be found in [10]. It consists of 𝑛𝑟 data inputs,
𝑟 selection signals and an output. It takes a value equal Right Shifter The shifter right moves the digits to
to the input line corresponding to the decoding of the the right by as many positions as specified in a dedicated
data word. The figure 8 shows the simplest MVL demux line. For integers this corresponds to performing a divi-
with 4 data lines and selection input SEL of data lines. sion of the number with respect to the base. Since these
To make the circuit, we used a selector block (module are components that can be used in series to perform op-
X2) that contains the 4 basic selectors. The output of the erations on multiple digits, we must provide for receiving
block determines which signal 𝑂𝑈 𝑇𝑖 of the circuit will and sending these digits to adjacent modules (figure 9).
end up in the 𝐼𝑁 input. The equation 17 describe the In the following examples, we will use 4-digit words, and
behavior of the output. the lines of communication with adjacent modules will
{︃ be 3. Indeed, the variable 𝑆𝐸𝐿 indicating the number of
𝐼𝑁 𝑖𝑓 𝑆𝑖 = 𝐿1 digits to be moved can take 4 values (including zero).
𝑂𝑈 𝑇𝑖 = (17)
𝐿0 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
Right Rotate Shifter In this section we wanted to
For example, if 𝑆𝐸𝐿 = 𝐿3 there will be 𝑆3 = 𝐿1 .
show the simplicity of implementation of a 4-digit word
The output signal from the selectors block 𝑋2 enables
rotation shifter. A selection input 𝑆𝐸𝐿 determines the
number of shifts in the word (figure 11).

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Figure 7: Encoder 16x2

Figure 8: MVL Demux 4x1

Figure 9: Collegamento in cascata di più shifter right

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Figure 10: Right Shifter

3.3. Sequential Circuits
A digital circuit is said to be sequential if the output de-
pends on the inputs applied and the state of the circuit. In
contrast, in combinational circuits the output is uniquely
determined by the values of the inputs. Thus, a sequen-
tial circuit has the ability to store information through
feedback in the circuits that allows the informative con-
tent calculated in the past to be brought back into the
input due to the non-instantaneous propagation times
in the semiconductors. We will then realize the D latch
circuit in MVL logic.
Figure 11: Right Rotate Shifter
D Latch The schema of the D latch is shown in figure
13, and it consists of two cascaded multiplexers in which
Left Shifter Similar to what we described for the the output of the first one determines the selection of the
right shifter, the left shifter moves the input signals to input of the second one. The data signal 𝐷 lands in all
the left. For integers it corresponds to a multiplication data inputs of the first mux except the input 𝐼𝑁0 . Indeed,
by the base. The figure 12 shows the circuit with 7 data in 𝐼𝑁0 comes the output data of the second mux. A clock
inputs and a selection signal 𝑆𝐸𝐿. In this case, each signal 𝐶𝐿𝐾, which intermittently takes on the values 𝐿0
module can expect the arrival of three digits from the and 𝐿1 , allows selection between the new data present
one located to its left. Meanwhile, the module under in 𝐷 (𝑆𝐸𝐿 ≥ 𝐿1 ) and the one previously calculated
consideration can shift three values of its base word to (𝑆𝐸𝐿 = 𝐿0 ).
the left. To verify the operation of the D latch, we used an
In this case if 𝑆𝐸𝐿 = 0, the most significant outputs articulated data signal (table 6) so as to check that the
are set to 𝐿0 , enabling the input 𝐼𝑁0 of the first three circuit had the desired behavior.
multiplexers on the left of the figure (𝑋8,𝑋10, 𝑋9). The
outputs 𝑂𝑈 𝑇6 , 𝑂𝑈 𝑇5 and 𝑂𝑈 𝑇4 are set to level zero. In
this case the inputs 𝐼𝑁1 ,𝐼𝑁2 ,𝐼𝑁3 do not compete with 4. Limits and Future Works
the outputs. As the value of the signal 𝑆𝐸𝐿 increases,
New circuits in multivalue logic may be a step toward
the inputs will be shifted to the left until 𝐼𝑁3 moves from
addressing the computational problems of certain appli-
the output 𝑂𝑈 𝑇3 to 𝑂𝑈 𝑇6 (𝑆𝐸𝐿 = 3) and three new
cations such as artificial intelligence and blockchain. The
signals will be present on 𝑂𝑈 𝑇0 , 𝑂𝑈 𝑇1 and 𝑂𝑈 𝑇3 .
amount of time, energy, and resources to deliver certain
services is increasing more and more, and traditional cir-
cuits seem unresponsive to current needs [21],[22], [23].
We presented several theoretical solutions, and many of

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Figure 12: Left Shifter

Figure 13: D Latch with MVL MUX 4+1

Figure 15: Testing D Latch: inputs

Figure 14: Testing D Latch

them are aligned with new technological solutions [24],
[25], such as mem-resistors [26] or programmable resis-
tor arrays in complex layers [27]. These last components
were developed by Massachusetts Institute of Technology
(MIT) to create neural networks to support a new area Figure 16: Testing D Latch: outputs
of artificial intelligence called analog deep learning.
The lack of integration of models developed with such
technologies is one of the limitations that must be over- employ bases that are powers of two; future efforts will
come to make the use of this logic effective. focus on this type of logic.
The first step in achieving the target of usability of such The proposed work has two important advantages over
logic within circuits is their integrability within current what has been produced in the literature on MVL sys-
systems in digital logic. To this end, it is desirable to tems:

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Table 6 The paper shows circuits that adopt the same represen-
Test Input Signals tation system as traditional binary digital ones, but im-
plement them using MVL signals (values). Among the
Time Volts
strengths of the presented solution, there is the scalabil-
0u 0.625 ity. Indeed, the presented approach is independent of the
30u 0.625 base used and thus of the number of levels.
31u 4.375 However, the gap with hardware technologies and tech-
60u 4.375 niques to support MVL, such as storing MVL values, is far
61u 1.875
from being closed. The previously mentioned inorganic
90u 1.875
91u 4.375 material, which makes the resistor extremely energy ef-
120u 4.375 ficient, is an example solution that could accelerate the
121u 1.875 industrialization of such circuits.
150u 1.875 One challenge for the further use of multi-valued logic
151u 3.125 in circuit design is the creation of an effective computer-
180u 3.125 aided design package. At present, many multi-core ar-
181u 0.625 chitectures have been developed and implemented, but
210u 0.625 although parallel computing resulting from multi-core
211u 4.375 architectures is a solution to increase the performance
240u 4.375
of a computer [32, 33, 34], with it arise various issues
241u 0.625
270u 0.625
related to the competition and collaboration of cores, es-
pecially when the latter are used in the neural networks
applications to the solution of different types of problems
[35, 36, 37, 38]. We can think of the problem of inaccu-
• The system we proposed has the ability to work
rate interrupts or information sharing in caches. Such
independently of the adopted base. Obviously,
issues are absent in a single computer operating with a
the choice of this value must be fixed through the
computing model close to that of a human.
trade-off between expressive power and the inter-
nal complexity of the circuits to be made. Just as
an example, being able to have a computer that References
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