Multi-Valued Logic Digital Circuits for Realizing a Complete Computer Architecture Alessandro Simonetta1 , Maria Cristina Paoletti1 and Alessio Venticinque2 1 Department of Enterprise Engineering, University of Rome Tor Vergata, Rome, Italy 2 Department of Electrical and Information Engineering, University of Naples Federico II, Napoli, Italy Abstract The objective of this paper is to lay the foundation for the construction of a computer architecture using entirely multivalue logic (MVL). To achieve this ambitious result, it is necessary to know how to design all the digital components that normally form the basis of a computerโ€™s operation. These are combinational circuits dedicated to mathematical computation and sequential circuits in charge of storing information. In the paper, a general methodology is proposed that can be used for the construction of digital circuits capable of working independently of the basis of representation of multivalue logic and the physical quantity used for encoding logical states. Keywords MVL, Multi-valued logic, CPU, Computer architecture, digital circuit, adder look ahead 1. Introduction ๐‘ The subject of multivalue logic as a natural evolution of ๐‘›โˆ‘๏ธโˆ’1 ๐‘โˆ’1 โˆ๏ธ representation in the binary system is a much debated ๐‘“ (๐‘ฅ ๐‘œ , ๐‘ฅ 1 , ..., ๐‘ฅ๐‘โˆ’1 ) = ๐‘˜ ๐‘– ยท ๐‘†๐‘๐‘— (๐‘–)(๐‘ฅ๐‘— ) (2) issue [1], [2]. Although various solutions, including tech- ๐‘–=0 ๐‘—=0 nological ones, have been proposed, but at present there where: is no calculator capable of operating in multivalued logic [3], [4], [5]. However, with the arrival of memresistors [6] โ€ข ๐‘˜๐‘– is the value taken at the i-th position in the and a multiplicity of multi-state semiconductor compo- combination, with ๐‘˜๐‘– โˆˆ T; nents, the scenario is evolving and the theory developed โ€ข ๐‘๐‘—(๐‘–) is the j-th digit of the number ๐‘–, represented in [7] could find easy application. The theory we are in base ๐‘› with ๐‘— โˆˆ {0, ..., ๐‘ โˆ’ 1}; going to describe is based on the extension of Boolean โ€ข ๐‘†๐‘๐‘— (๐‘–) is the value selector ๐‘๐‘— (๐‘–) applied to algebra and the binary numbering system toward an operand ๐‘ฅ๐‘— with ๐‘— โˆˆ {0, ..., ๐‘ โˆ’ 1} e ๐‘– โˆˆ ๐‘›-valued (discrete) numbering system [8], [9]. In this {0, ..., ๐‘›๐‘ โˆ’ 1}; paper we will start from the theoretical definition and gradually go on to realize all the digital components that Thus, to express any MVL function ๐‘“ , p+2 basis function characterize a traditional computer architecture. are sufficient: ๐‘ selection, addition and multiplication functions. 2. Method 2.1. The selection functions The proposed method use the teory in [10]. Assum- The selection functions ๐‘†๐‘– with ๐‘– โˆˆ {0, ..., ๐‘›โˆ’1}, that we ing that we have a domain of discrete values T = can call Selectors too, are unary functions. We can define {0, 1, .., ๐‘› โˆ’ 1}, we can easily show that any function ๐‘“ : as many selectors as there are symbols in the domain T. ๐‘“ : T ร— ... ร— T โ†’ T (1) ๐‘†๐‘– : T โ†’ B (3) can be expressed as a linear combination of the input A selector is able to check whether the value of the variables: operand matches a value in the set T: {๏ธƒ ICYRIME 2022: International Conference of Yearly Reports on Infor- 1 ๐‘ ๐‘’ ๐‘ก = ๐‘– matics, Mathematics, and Engineering. Catania, August 26-29, 2022 ๐‘†๐‘– (๐‘ก) = (4) " alessandro.simonetta@gmail.com (A. Simonetta); 0 ๐‘ ๐‘’ ๐‘ก ฬธ= ๐‘– mariacristina.paoletti@gmail.com (M. C. Paoletti)  0000-0003-2002-9815 (A. Simonetta); 0000-0001-6850-1184 with ๐‘–, ๐‘ก โˆˆ {0, ..., ๐‘› โˆ’ 1}. Using the selection functions, (M. C. Paoletti); 0000-0003-3286-3137 (A. Venticinque) any combination of the input variables can be identified. ยฉ 2022 Copyright for this paper by its authors. Use permitted under Creative Commons License Attribution 4.0 International (CC BY 4.0). For example, to check if all variables ๐‘ฅ0 , ..., ๐‘ฅ๐‘โˆ’1 have CEUR Workshop Proceedings http://ceur-ws.org ISSN 1613-0073 CEUR Workshop Proceedings (CEUR-WS.org) 78 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 the value ๐‘› โˆ’ 1 except ๐‘ฅ0 which must be equal to 1, we 3. MVL digital circuits can use the following function: In this section, we will see how it is possible to construct all the circuits that form the basis of a traditional com- ๐œ‘ = ๐‘†1 (๐‘ฅ0 ) ยท ๐‘†๐‘โˆ’1 (๐‘ฅ1 ) ยท ... ยท ๐‘†๐‘โˆ’1 (๐‘ฅ๐‘โˆ’1 ) (5) puter architecture [11], [12]. Thus, we will start with combinational circuits, those in which the output is a which returns the value 1 exclusively in the case where function of the inputs, and then we will consider the the input variables meet the requirement: smallest memory element, the D Latch. To accomplish this task we will use the same architectural choice made (๐‘ฅ0 , ..., ๐‘ฅ๐‘โˆ’1 ) = (1, ๐‘› โˆ’ 1, ..., ๐‘› โˆ’ 1) (6) in [10], and supported by studies in [13], thus a logic based on 4 values that coincides with the base-4 num- 2.2. Sum bering system. The four logic values will be represented through the voltage levels as reported in table 1. Let us consider the summation of equation 2, we observe that only one term in the summation will be valued at ๐‘˜๐‘ค corresponding to the coding in base ๐‘› of ๐‘ค. Indeed, all Table 1 the terms of the summation are null except the one corre- MVL levels sponding to the combination identified by the selection Interval Logic level ๐‘‰๐‘–๐‘‘๐‘’๐‘Ž๐‘™ functions: ๐‘‰๐‘š๐‘–๐‘› โ‰ฅ ๐‘‰๐‘š๐‘Ž๐‘ฅ < ๐‘“ (๐‘ฅ๐‘œ , ๐‘ฅ1 , ..., ๐‘ฅ๐‘โˆ’1 ) = ๐‘˜๐‘ค (7) ๐ฟ0 0 1.25 0.625 ๐ฟ1 1.25 2.50 1.875 2.3. Multiplication ๐ฟ2 2.50 3.75 3.125 ๐ฟ3 2.50 5.00 4.375 With reference to the generic term of the summation of the equation 2, it can be expressed by a function ๐œ‘: We also studied the behavior of the proposed circuits by verifying the limits of the adopted components [14], ๐œ‘ : T ร— B ร— ... ร— B โ†’ T (8) [15], [16]. In particular, the details for the configuration that is equivalent to ๐œƒ: of the components are the following: ๐œƒ :Tร—Bโ†’B (9) โ€ข AND and OR logic gates: โ€“ Td = 10n thus: โ€“ Ref = 0.5 โ€“ Trise = 5n ๐‘ก ยท ๐‘0 ยท ๐‘1 ยท ... ยท ๐‘๐‘โˆ’1 = ๐‘ก ยท (๐‘0 ยท ๐‘1 ยท ... ยท ๐‘๐‘โˆ’1 ) = ๐‘ก ยท ๐‘ (10) โ€“ Tfall = 5n Indeed, it is sufficient to make a function with two โ€“ Vhigh = 5 operands: one MVL and the other binary. This function โ€ข inverted gates: returns as output the value of the multivalue input (if โ€“ Td = 5n the binary value is unity) or zero in the other case: โ€“ Ref = 0.5 โ€“ Trise = 5n {๏ธƒ 0 ๐‘ ๐‘’ ๐‘ = 0 ๐œƒ(๐‘, ๐‘ก) = (11) โ€“ Tfall = 5n ๐‘ก ๐‘ ๐‘’ ๐‘ = 1 โ€“ Vhigh = 5 with ๐‘ก โˆˆ T and ๐‘ โˆˆ B. Recalling that the logical conjunction operation returns a result that is equivalent to multiplication between bits 3.1. LTSpice (the result is one if and only if all the operands are 1), we The electronic circuits that we will describe, were de- can conclude that it is possible to use the AND operator signed and validated using the product LTspiceยฎ XVII by to compute the value ๐‘ in the binary domain. At this Analog Device Corporation [17], distributed on the devel- point it is possible to use that bit to calculate the MVL operโ€™s website. This simulator has a graphical interface function ๐œƒ(๐‘, ๐‘ก). Without loss of generality and with the to build the schematics and allows the user to test the purpose of making the paper easier to read, we will use circuits. The tool also allows new features to be defined the symbol normally used for multiplication to denote the and imported as elements in the various schemes. There- function ๐œƒ conscious of the fact that it is multiplication fore, we chose to reuse the circuit diagrams proposed in between values pertaining to different domains (B โŠ† T). [10] regarding the selectors, multiplexer and half-adder to design new ones. 79 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 3.2. Combinational Circuits Table 2 MVL true table: adding single MVL digits ๐ด๐‘– ๐ต๐‘– ๐ถ๐‘– ๐‘†๐‘– ๐ถ๐‘–+1 ๐‘”๐‘– ๐‘๐‘– 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 2 0 0 0 0 2 0 2 0 0 0 0 2 1 3 0 0 0 0 3 0 3 0 0 0 0 3 1 0 1 0 1 1 0 0 1 0 0 0 Figure 1: Look-ahead full adder single digit detail 1 0 1 2 0 0 0 1 1 0 2 0 0 0 1 1 1 3 0 0 0 1 2 0 3 0 0 0 1 2 1 0 1 0 1 1 3 0 0 1 1 0 1 3 1 1 1 1 0 2 0 0 2 0 0 0 2 0 1 3 0 0 0 2 1 0 3 0 0 0 2 1 1 0 1 0 1 2 2 0 0 1 1 0 2 2 1 1 1 1 0 2 3 0 1 1 1 0 2 3 1 2 1 1 0 3 0 0 3 0 0 0 3 0 1 0 1 0 1 3 1 0 0 1 1 0 3 1 1 1 1 1 0 3 2 0 1 1 1 0 3 2 1 2 1 1 0 3 3 0 2 1 1 0 3 3 1 3 1 1 0 with ๐ด๐‘– , ๐ต๐‘– , ๐‘†๐‘– โˆˆ T and ๐ถ๐‘– , ๐ถ๐‘–+1 , ๐‘”๐‘– , ๐‘๐‘– โˆˆ B MVL look-ahead adder In this section we will study the behavior of the circuit MVL look-ahead adder of 4- Figure 2: Look-ahead full adder blocks scheme digit base-4 words. In [7] a half-adder consisting of two inputs and two outputs in base 4 has already been pre- sented, and starting from this circuit the authors design as indicated in table 3. a full-adder in [10]. The most obvious problem with this circuit is the response time, which depends on the prop- Table 3 agation delay of the carryover in the various half-adders. Adding two MVL words of ๐‘ž length The time grows as the number of digits of operands and thus half-adders used to construct the adder increases ๐ถ๐‘ž ๐ถ๐‘žโˆ’1 ... ๐ถ0 ๐ด๐‘žโˆ’1 ... ๐ด0 + [18], [19]. Indeed, in a look-ahead adder the carryover ๐ต๐‘žโˆ’1 ... ๐ต0 = is not affected by the delay of circuit elements placed in cascade. Consider two MVL words of length ๐‘ž: ๐‘†๐‘ž ๐‘†๐‘žโˆ’1 ... ๐‘†0 ๐ด = {๐ด๐‘žโˆ’1 , ..., ๐ด0 } and ๐ต = {๐ต๐‘žโˆ’1 , ..., ๐ต0 }, if the calculated carryovers are ๐ถ = {๐ถ๐‘ž , ..., ๐ถ1 } and ๐ถ0 is If by the variables ๐‘๐‘– and ๐‘”๐‘– we denote the generated the potential carryover of a previous least significant and propagated carryover, respectively, we can build the word, we can calculate the sum word ๐‘† = {๐‘†๐‘ž , ..., ๐‘†0 } truth table (table 2) related to the sum of two generic 80 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Figure 3: Look-ahead adder with 4 MVL digits MVL digits. The values of ๐‘๐‘– and ๐‘”๐‘– are given by the a switch driven by a binary signal, can send the value relation 12 for a cirucite in which the signals are in basecorresponding to ๐ฟ1 to the second half-adder. The adder n. circuit will use two half-adders to calculate ๐‘†๐‘– = ๐ถ๐‘– + {๏ธƒ ๐ด๐‘– + ๐ต๐‘– ; the variable ๐‘”๐‘– will be calculated from the first 0 ๐‘–๐‘“ ๐ด๐‘– + ๐ต๐‘– โ‰ค ๐‘› โˆ’ 1 half-adder while ๐‘๐‘– will be calculated using the selection ๐‘”๐‘– = (12) 1 ๐‘–๐‘“ ๐ด๐‘– + ๐ต๐‘– > ๐‘› โˆ’ 1 function to understand whether ๐ด๐‘– + ๐ต๐‘– = ๐‘› โˆ’ 1 (figure {๏ธƒ 1). This component will be replicated for each couple of 0 ๐‘–๐‘“ ๐ด๐‘– + ๐ต๐‘– = ๐‘› โˆ’ 1 input in order to build a look-ahead adder as in figure ๐‘๐‘– = (13) 2. In figure 3 a look-ahead adder circuit with 4 MVL 1 ๐‘–๐‘“ ๐ด๐‘– + ๐ต๐‘– ฬธ= ๐‘› โˆ’ 1 digits is made. This circuit can be used to perform MLV In the same way, in the case of the MVL, we can determine word sum with lengths multiple of 4: for example, we can in advance the values of the carryovers ๐ถ โˆ‘๏ธ€๐‘–+1 from โˆ๏ธ€ the add up 8 MVL digits by cascading two circuits (figure 4). variables ๐‘”๐‘– and ๐‘๐‘– . Using the symbols and , for The behavior of the circuit is verified through a concrete logical disjunction (OR) and logical conjunction (AND), example: suppose we add the value ๐ด = 310200023 respectively, we can write the equation 14. with ๐ต = 33212131 and that the carryover ๐ถ0 will be 0. The expected result is the number S=130232220 as can ๐‘– ๐‘–โˆ’1 ๐‘– โˆ๏ธ โˆ‘๏ธ โˆ๏ธ be easily seen from the calculation shown in the table 4. ๐ถ๐‘–+1 = ๐‘”๐‘– + ๐ถ0 ๐‘๐‘— + ๐‘”๐‘˜ ๐‘๐‘— (14) ๐‘—=0 ๐‘˜=0 ๐‘—=๐‘˜+1 Decoder A decoder is a combinational circuit with ๐‘Ÿ However, the values of the carryovers (๐ถ๐‘–+1 ), determined inputs and ๐‘›๐‘Ÿ outputs. It returns as output the decoded in such a way, are in the binary domain, instead we need form of a coded word given as input. the value corresponding to the logical level ๐ฟ1 of the table Starting with the most basic decoder, which decodes a 1. Then a transduction element is needed that, through single digit in the four possible values, we will construct 81 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Figure 4: Look-ahead adder with 8 MVL digits Table 4 Table 5 An example of two words sum of 8 MVL digits MVL True Table 1 1 1 1 ๐ผ๐‘ ๐‘†0 ๐‘†1 ๐‘†2 ๐‘†3 3 1 0 2 0 0 2 3 + 3 3 2 1 2 1 3 1 = ๐ฟ0 ๐ฟ1 ๐ฟ0 ๐ฟ0 ๐ฟ0 ๐ฟ1 ๐ฟ0 ๐ฟ1 ๐ฟ0 ๐ฟ0 1 3 0 2 3 2 2 2 0 ๐ฟ2 ๐ฟ0 ๐ฟ0 ๐ฟ1 ๐ฟ0 ๐ฟ3 ๐ฟ0 ๐ฟ0 ๐ฟ0 ๐ฟ1 the decoder that decodes two-digit words. Making a single-digit decoder is a simple task because it is sufficient Since we have two one-value decoders, it is possible to to use the selection functions by applying them to the construct a decoder with ๐‘Ÿ = 2 and 42 = 16 outputs (fig- same input (figure 5). ure 6) using an AND gates array that realizes all possible combinations of pairs relative to the outputs of the two decoders. The figure 6 shows the circuit with the compo- nents X2 and X3 representing single-digit decoders. In this case, if the input is the number 134 (๐ผ๐‘1 = ๐ฟ1 and ๐ผ๐‘0 = ๐ฟ3 ) the only enabled digit in output would be ๐‘‚7 (logic level ๐ฟ1 ) . Figure 5: MVL Decoder 1x4 Encoder The encoder is a combinational circuit too, {๏ธƒ that receives as input ๐‘›๐‘Ÿ MVL digits and returns as output ๐ฟ1 ๐‘–๐‘“ ๐ผ๐‘ = ๐‘– ๐‘Ÿ MVL digits. It performs the opposite function to the ๐‘†๐‘– (๐ผ๐‘ ) = (15) ๐ฟ0 ๐‘–๐‘“ ๐ผ๐‘ ฬธ= ๐‘– decoder: it receives a decoded representation as input and provides the corresponding encoding as output. The Based on the value of the input IN, it will select the cor- figure 14 shows an encoder with 16 inputs and 2 outputs. responding output (level ๐ฟ1 ), while all other outputs will Each ๐ผ๐‘๐‘– input passes through a ๐‘†๐‘– switch that detects be zero (level ๐ฟ0 ), according to what reported in table 5. the ๐ฟ1 level at the input (equation 16). 82 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Figure 6: MVL Decoder 2x16 {๏ธƒ the corresponding switch by propagating the IN signal ๐ฟ1 ๐‘–๐‘“ ๐ผ๐‘๐‘– = ๐ฟ1 to the output ๐‘‚๐‘ˆ ๐‘‡3 . ๐‘†1 (๐ผ๐‘๐‘– ) = (16) ๐ฟ0 ๐‘œ๐‘กโ„Ž๐‘’๐‘Ÿ๐‘ค๐‘–๐‘ ๐‘’ Shifter In this section we will look exclusively at To make the circuit simpler, we grouped the selector parallel-type shifters, which are normally used to per- switch outputs that would determine the same value on form mathematical operations (e.g. multiplication and the output signals ๐‘‚๐‘ˆ ๐‘‡ 1 and ๐‘‚๐‘ˆ ๐‘‡ 2. Note that the division by base). In general, having a summation and a output of each enabled switch causes its closure, which shifter makes it possible to perform multiplication and brings the output level value. For example, if ๐ผ๐‘ 7 = ๐ฟ1 division operations for general numbers as long as they the output of selector ๐‘†๐ธ๐ฟ8 enables the OR gates that are expressed in terms of the base [20]. An example determine ๐‘‚๐‘ˆ ๐‘‡ 1 = ๐ฟ1 and ๐‘‚๐‘ˆ ๐‘‡ 0 = ๐ฟ3 . of multiplication between 17 and a generic number ๐‘ฅ, with ๐‘ฅ โˆˆ N, performed through the use of shifting and Demultiplexer The demultiplexer (or simply demux) addition, is given in the equation 18. is a circuit typically used to restore multiplexing pro- duced by a multiplexer in communications. Its treatment 17 ยท ๐‘ฅ = (41 + 40 ) ยท ๐‘ฅ = 41 ยท ๐‘ฅ + 40 ยท ๐‘ฅ (18) in MVL can be found in [10]. It consists of ๐‘›๐‘Ÿ data inputs, ๐‘Ÿ selection signals and an output. It takes a value equal Right Shifter The shifter right moves the digits to to the input line corresponding to the decoding of the the right by as many positions as specified in a dedicated data word. The figure 8 shows the simplest MVL demux line. For integers this corresponds to performing a divi- with 4 data lines and selection input SEL of data lines. sion of the number with respect to the base. Since these To make the circuit, we used a selector block (module are components that can be used in series to perform op- X2) that contains the 4 basic selectors. The output of the erations on multiple digits, we must provide for receiving block determines which signal ๐‘‚๐‘ˆ ๐‘‡๐‘– of the circuit will and sending these digits to adjacent modules (figure 9). end up in the ๐ผ๐‘ input. The equation 17 describe the In the following examples, we will use 4-digit words, and behavior of the output. the lines of communication with adjacent modules will {๏ธƒ be 3. Indeed, the variable ๐‘†๐ธ๐ฟ indicating the number of ๐ผ๐‘ ๐‘–๐‘“ ๐‘†๐‘– = ๐ฟ1 digits to be moved can take 4 values (including zero). ๐‘‚๐‘ˆ ๐‘‡๐‘– = (17) ๐ฟ0 ๐‘œ๐‘กโ„Ž๐‘’๐‘Ÿ๐‘ค๐‘–๐‘ ๐‘’ Right Rotate Shifter In this section we wanted to For example, if ๐‘†๐ธ๐ฟ = ๐ฟ3 there will be ๐‘†3 = ๐ฟ1 . show the simplicity of implementation of a 4-digit word The output signal from the selectors block ๐‘‹2 enables rotation shifter. A selection input ๐‘†๐ธ๐ฟ determines the number of shifts in the word (figure 11). 83 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Figure 7: Encoder 16x2 Figure 8: MVL Demux 4x1 Figure 9: Collegamento in cascata di piรน shifter right 84 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Figure 10: Right Shifter 3.3. Sequential Circuits A digital circuit is said to be sequential if the output de- pends on the inputs applied and the state of the circuit. In contrast, in combinational circuits the output is uniquely determined by the values of the inputs. Thus, a sequen- tial circuit has the ability to store information through feedback in the circuits that allows the informative con- tent calculated in the past to be brought back into the input due to the non-instantaneous propagation times in the semiconductors. We will then realize the D latch circuit in MVL logic. Figure 11: Right Rotate Shifter D Latch The schema of the D latch is shown in figure 13, and it consists of two cascaded multiplexers in which Left Shifter Similar to what we described for the the output of the first one determines the selection of the right shifter, the left shifter moves the input signals to input of the second one. The data signal ๐ท lands in all the left. For integers it corresponds to a multiplication data inputs of the first mux except the input ๐ผ๐‘0 . Indeed, by the base. The figure 12 shows the circuit with 7 data in ๐ผ๐‘0 comes the output data of the second mux. A clock inputs and a selection signal ๐‘†๐ธ๐ฟ. In this case, each signal ๐ถ๐ฟ๐พ, which intermittently takes on the values ๐ฟ0 module can expect the arrival of three digits from the and ๐ฟ1 , allows selection between the new data present one located to its left. Meanwhile, the module under in ๐ท (๐‘†๐ธ๐ฟ โ‰ฅ ๐ฟ1 ) and the one previously calculated consideration can shift three values of its base word to (๐‘†๐ธ๐ฟ = ๐ฟ0 ). the left. To verify the operation of the D latch, we used an In this case if ๐‘†๐ธ๐ฟ = 0, the most significant outputs articulated data signal (table 6) so as to check that the are set to ๐ฟ0 , enabling the input ๐ผ๐‘0 of the first three circuit had the desired behavior. multiplexers on the left of the figure (๐‘‹8,๐‘‹10, ๐‘‹9). The outputs ๐‘‚๐‘ˆ ๐‘‡6 , ๐‘‚๐‘ˆ ๐‘‡5 and ๐‘‚๐‘ˆ ๐‘‡4 are set to level zero. In this case the inputs ๐ผ๐‘1 ,๐ผ๐‘2 ,๐ผ๐‘3 do not compete with 4. Limits and Future Works the outputs. As the value of the signal ๐‘†๐ธ๐ฟ increases, New circuits in multivalue logic may be a step toward the inputs will be shifted to the left until ๐ผ๐‘3 moves from addressing the computational problems of certain appli- the output ๐‘‚๐‘ˆ ๐‘‡3 to ๐‘‚๐‘ˆ ๐‘‡6 (๐‘†๐ธ๐ฟ = 3) and three new cations such as artificial intelligence and blockchain. The signals will be present on ๐‘‚๐‘ˆ ๐‘‡0 , ๐‘‚๐‘ˆ ๐‘‡1 and ๐‘‚๐‘ˆ ๐‘‡3 . amount of time, energy, and resources to deliver certain services is increasing more and more, and traditional cir- cuits seem unresponsive to current needs [21],[22], [23]. We presented several theoretical solutions, and many of 85 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Figure 12: Left Shifter Figure 13: D Latch with MVL MUX 4+1 Figure 15: Testing D Latch: inputs Figure 14: Testing D Latch them are aligned with new technological solutions [24], [25], such as mem-resistors [26] or programmable resis- tor arrays in complex layers [27]. These last components were developed by Massachusetts Institute of Technology (MIT) to create neural networks to support a new area Figure 16: Testing D Latch: outputs of artificial intelligence called analog deep learning. The lack of integration of models developed with such technologies is one of the limitations that must be over- employ bases that are powers of two; future efforts will come to make the use of this logic effective. focus on this type of logic. The first step in achieving the target of usability of such The proposed work has two important advantages over logic within circuits is their integrability within current what has been produced in the literature on MVL sys- systems in digital logic. To this end, it is desirable to tems: 86 Alessandro Simonetta et al. CEUR Workshop Proceedings 78โ€“89 Table 6 The paper shows circuits that adopt the same represen- Test Input Signals tation system as traditional binary digital ones, but im- plement them using MVL signals (values). Among the Time Volts strengths of the presented solution, there is the scalabil- 0u 0.625 ity. Indeed, the presented approach is independent of the 30u 0.625 base used and thus of the number of levels. 31u 4.375 However, the gap with hardware technologies and tech- 60u 4.375 niques to support MVL, such as storing MVL values, is far 61u 1.875 from being closed. The previously mentioned inorganic 90u 1.875 91u 4.375 material, which makes the resistor extremely energy ef- 120u 4.375 ficient, is an example solution that could accelerate the 121u 1.875 industrialization of such circuits. 150u 1.875 One challenge for the further use of multi-valued logic 151u 3.125 in circuit design is the creation of an effective computer- 180u 3.125 aided design package. At present, many multi-core ar- 181u 0.625 chitectures have been developed and implemented, but 210u 0.625 although parallel computing resulting from multi-core 211u 4.375 architectures is a solution to increase the performance 240u 4.375 of a computer [32, 33, 34], with it arise various issues 241u 0.625 270u 0.625 related to the competition and collaboration of cores, es- pecially when the latter are used in the neural networks applications to the solution of different types of problems [35, 36, 37, 38]. We can think of the problem of inaccu- โ€ข The system we proposed has the ability to work rate interrupts or information sharing in caches. Such independently of the adopted base. Obviously, issues are absent in a single computer operating with a the choice of this value must be fixed through the computing model close to that of a human. trade-off between expressive power and the inter- nal complexity of the circuits to be made. Just as an example, being able to have a computer that References works in hexadecimal would make it possible to reduce the size of memory communication lines, [1] E. Dubrova, Multiple-Valued Logic in VLSI: and to perform calculations directly in hexadec- Challenges and Opportunities, Proceedings of imal base by a factor of 4. On the other hand, NORCHIPโ€™99 (1999). the number of switches in the decoder shown [2] D. Etiemble, 45-year CPU Evolution: one law and in figure 6 would increase from 16 to 256 ele- two equations, Second Workshop on Pioneering ments. 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