In the last year, physical working Quantum Computers have been built and made available for the end users. Such devices, working under the rules of Quantum Mechanics, can only apply a finite set of one/two qubit operations that form a universal set of gates. Single qubit gates are fault-tolerant, while the same cannot be said for two qubit gates. Hence, unitary matrices adopted in Quantum Algorithms must be synthesized in terms of this universal set of operations to obtain a quantum circuit. This synthesis procedure, however, is not constraint-free. In fact, we prefer circuits with minimum number of qubits and with minimum circuit depth. Cliford+T universal set is one of the most adopted in the literature for synthesis. In such set we have 3 single qubit gates and the CNOT, which is a two qubit gate. Many eforts have been directed to devise algorithms that synthesize general unitary matrices into Cliford+T circuits. These algorithms usually tend to optimize circuit depth or eventually the number of T gates. Since two qubit gates are not fault tolerant, in this work we propose an ASP based technique to minimize the number of CNOT gates inside a Cliford+T circuit. We start from a SAT encoding of the problem, and we translate it into an ASP model over a graph, by first working with a generic graph, and then by adopting the structure of a layered DAG. We provide experimental evidence of the scalability of our proposal.
In the last few years, a lot of efort has been put into Quantum Computing from both academia
and companies. One of the goals is to increase the number of qubits Quantum Computers
are able to manage. In fact, the so called Quantum speed-up [
Assuming that we have solved the problem of manipulating a reasonable amount of qubits, it remains to consider the dificulty of compiling a quantum algorithm over a real physical device. We take into account Quantum Computers that are built using the superconducting qubits technology. In such architecture, qubits are edited using gates—unitary matrices. Nevertheless, not all unitary operations can be directly implemented in physical hardware. Up to now, only single and two qubit gates can be physically manufactured. The former are more reliable, but may still fail. The latter are error prone in the superconducting qubit environment, while are more reliable in architectures like photonics or Rydberg atoms. The operations that can be physically applied in a Quantum Computer are called base of gates. When a generic unitary matrix ∈ C2× 2 has to be applied to a physical set of qubits, it must be rewritten in terms of given base of gates, i.e., it has to be synthesized. If a base can synthesize correctly any unitary ∈ C2× 2 , then it is called an universal set of gates. Once a universal set of gates ℬ is defined, the problem of rewriting a given unitary in terms of ℬ is called synthesis. This problem has a complexity that is polynomial in the size of the input unitary. Hence, it has a Ω(2) lower bound running time.
Anyway, a lot of efort has been put to create algorithms that synthesize any unitary in a reasonable time and with a low circuit depth and width — often being satisfied with an approximated synthesis. The circuit depth is the length of the circuit, while the width is another term for the number of qubits used. The former has to be kept low since the coherence time of quantum states is not really high, hence circuits that are too long are doomed to fail in their computation. The latter is strictly related to the issue we addressed at the beginning: number of qubits in physical Quantum Computers is currently limited.
Most of the synthesis algorithms are devised using the Cliford+T set of universal gates.
Such set is composed by 3 single qubit gates and a two qubits gate. Diferent techniques have
been adopted for the synthesis problem. For example, exact techniques with QMDD have been
proposed in [
Sometimes, it is also reasonable to think about sub-problems that arise from the synthesis
of circuits. One idea can be to focus into the minimization of the number of occurrences of
one type of gate inside a universal set. In [
This kind of problem is really important since the CNOT gate is the only two qubits gate in the Cliford+T base set. Two qubits gates cannot be physically implemented without introducing errors. Hence, their minimization could also lead to a reduction of the efort required for Quantum Error Correction [9].
For this reason, we consider the same problem as in [8], but we try to solve it with a diferent approach. We take as input a T-optimal circuit made only of CNOT and T gates. We want to produce a circuit ′ that preserves the behaviour of and with the minimum number of CNOT gates. The approach in [8] starts by reducing the problem to a classical one using the notion of phase polynomial representation. Secondly, a satisfiability model is developed to obtain a solution to the following problem: can the circuit be written with CNOT gates?. Hence, the model is queried for each possible value of starting from 1. When the first solution is found, it is given as output. Starting from this solution, we decided to propose a solution to the same problem with two major diferences. The first is to encode the problem in an Answer Set Programming model instead that using a SAT encoding. The second is to use ASP solvers properties to find the minimum number of CNOT gates, without doing an iteratively approach as in [8].
The paper is structured as follows: Section 2 contains the definition of the problem and its translation to a classical one. Some results about circuit synthesis coming from the literature are presented in Section 3. Section 4 and Section 5 are used to describe the two diferent encodings we propose to solve the given problem. After that, Section 6 is devoted to experimental evaluation. Some conclusions and ideas for future works are drawn in Section 7. For space reason we omit the introduction of ASP, the reader may refer to [10].
Modern Quantum Computers (like Osprey from IBM) have two important limits: • Only a finite set of operations can be applied to the qubit • The quantum coherence can be maintained for a short amount of time The finite set of operations a Quantum Computer can apply is usually called
The process of rewriting in terms of gates of a Universal Set of Gates is called synthesis.
The most used Universal Set of Gates for synthesis is the Cliford + T, which contains the following single qubit gates: = √ 1 (︂ 1
1 )︂ 2 = ⎜⎜⎝00 10 00 01⎟⎠⎟
0 0 1 0 (, ) = (, ⊕ ) where , are the control and the target of the CNOT gate, respectively. Its efect is twofold: • it leaves the control qubit unchanged • the target is flipped if the control is 1 — a XOR between control and target Single qubit gates can be implemented in physical quantum computers with no errors. On the other hand, two qubit gates introduce error that must be corrected using Quantum Error Correction (QEC) techniques. Hence, it is reasonable to think about synthesis techniques that aim at minimizing the number of CNOT gates in the resulting circuit.
In this paper, we will start from a circuit made of CNOT and T gates (same problem tackled in [8]), and we will minimize the number of CNOT gates. To do so, we first turn a Quantum problem, into a classical one using the following definition from [11]: Definition 1 (phase polynomial representation). The action of a {CNOT, T} circuit on the initial state |1, 2, · · · ⟩ has the form:
|1, 2, · · · ⟩ ↦→ 4 (1,2,· ,) |(1, 2, · · · )⟩ with (1, 2, · · · , ) defined as: =1 (1, 2, · · · , ) = ∑︁( mod 8)(1, 2, · · · ) → B is a linear reversible function and is a linear combination of linear boolean where : B functions : B
→ B.
The coeficients
(reduced modulo 8) measure the number of / 4 rotations applied to each . The number represents the number of T gates in the circuit.
Each circuit has its phase polynomial representation, uniquely defined by
, , for = 1, 2, . . . .
More than one {CNOT, T} circuit can share the same phase polynomial representation.
Since is a linear reversible function with inputs and outputs, it can be written as a × boolean matrix . On the other hand, each can be expressed as a boolean row vector . Example 1. Consider the following circuit: 1 2 3
• INPUT: , 1, 2, · · · • OUTPUT: a sequence of CNOT gates to be applied such that the final behaviour of the circuit is the one described by .
The constraints we must fulfill are the following: • We can only apply CNOT gates • For each with ∈ {1, 2, · · · , }, there must exist a moment during the computation in which a row of is exactly .
The two constraints allow us to avoid caring about the gates. We just have to create the correct slots for them to be applied, but nothing more.
We must find a circuit such that 1 and 3 are unchanged while 2 becomes the XOR of all the three variables. Moreover, it must be true that at some point one of the variables must be the XOR between 1 and 2 to match the constraint on 1.
The following circuit, made only of CNOT gates, solves the problem.
1 2 3 1 1
We pointed out with the red line the moment in which the constraint on 1 is satisfied.
Circuit synthesis has become a more and more prominent problem since the first physically working quantum computers were manufactured. A generic synthesis algorithm takes two inputs: a generic unitary matrix ∈ C2× 2 and a universal set of gates ℬ. The output must be a circuit made only of gates from ℬ that implements exactly . Clearly, we are not interested in any type of circuit. We are interested in keeping the circuit (i) as short as possible, because of the very volatile qubits state, (ii) as thin as possible to use the minimum number of qubits.
Diferent approaches and algorithms have been proposed. A large branch of them is composed
by the ones using Quantum Multivalued Decision Diagrams (QMDD) [
QMDDs have been introduced as a means for the eficient representation and manipulation of quantum gates and circuits. The fundamental idea is a recursive partitioning of the respective transformation matrix and the use of edge and vertex weights to represent various complex-valued matrix entries. More precisely, a transformation matrix of dimension 2 × 2 is successively partitioned into four sub-matrices of dimension 2− 1 × 2− 1. This partitioning is represented by a directed acyclic graph - the QMDD.
In [
Not only exact algorithms have been defined. In [
Synthesis problem of Cliford+T circuits is not always addressed as one big problem. A lot of authors also tackled some sub-problems like the minimization with respect to one single gate in the universal set. One example is the minimization of the CNOT gates.
For such problem, an algebraic approach is given in [13] where the authors start by first describing the group structure underlying quantum circuits generated by CNOT gates. Such results are then exploited to create heuristics useful to reduce the number of CNOT in circuits.
A technique based on Steiner Trees has been adopted in [14]. In this case, the authors also took into account the problem of the actual neighbour relation between qubits. When working with physical quantum devices, not every qubit is connected to all the others. Hence, when applying a CNOT between two qubits, we must be sure that these two qubits are linked. Otherwise, we must apply also swap gates, which correspond to 3 CNOT gates.
Last but not least, the SAT based approach has been proposed in [8]. Authors aimed at minimizing the number of CNOT gates in a circuit by setting up the solution of a satisfiability problem. Such solution is then iteratively queried until a first feasible model is found and returned as result to the main problem. The SAT solver will eventually be queried for at most 2 times, where is the number of qubits, because of this the following result from [15]: Theorem 1. Any n-qubit circuit of CNOT gates is equivalent to one composed of at most 2 gates.
A SAT encoding is used also in [16]. The authors noticed that synthesis can be related to the problem of finding best boolean chains to represent functions. Hence, they proposed a DAG based approach to generate all possible DAG structures with a fix number of nodes and then query the satisfiability model to check if such structure would solve the problem.
The first model we propose is a graph based one. The circuit from Example 1 (without the gates) can be interpreted as the labelled graph = (, ) depicted in Figure 1. 1 1 2 2 3
CNOT gates are encoded as labelled edges. The first CNOT to apply is the one with control 1 and target 2, encoded by the edge labelled 1. The second CNOT has control 2 and target 3, and it is encoded by the edge labelled 2.
Edge = (, , ℎ) means that the ℎ-th CNOT to apply in the circuit has as control and as target. Such edge is represented as: 2 2 1
1 2 ℎ This idea can be generalized to any CNOT circuit.
We solve the problem introduced in Section 2 by computing = (, ) starting from ∈ {0, 1}× and a set of . The set of nodes is always {1, 2, · · · }. Our aim is to build the set of minimum size .
First of all, it must hold that for each time step ≤ , exactly one edge labelled must exist. After all the steps, the following has to be true: val() = ∀ ∈ {1, 2, · · · , } where val is defined as follows: val0() = val() = val− 1() val() = val− 1() ⊕ val− 1() ∀ ∈ {1, 2, · · · , } if ∄ | (, , ) ∈ ∧ > 0 if ∃ | (, , ) ∈ ∧ > 0
With the notation ∈ val(), we mean that the XOR operation described by val() contains .
The above constraint was necessary to ensure that the final circuit respects the limitations imposed by .
As far as is concerned, the following must hold:
∀ ∃ ≤ ∃ | val() = Example 3. Suppose and 1 are defined as in Example 2. Then the graph depicted in Figure 2 is the one obtained with our model:
The val of 1 and 3 evolves as follows: val0(1) = val1(1) = val2(1) = 1 = (1 0 0) val0(3) = val1(3) = val2(3) = 3 = (0 0 1) while for 2 we obtain:
The problem is solved since val2() = for every and val1(2) = 1. 4.1. Encoding in clingo We now briefly describe how we encoded the aforementioned solution in the clingo solver.
The input has been encoded in a very simple way. We provide the model with (the size of ) and , the number of diferent . Then, with a predicate of the form g(, , ) we describe the matrix , with the following rules: , = 1 ↔ g(, , 1) , = 0 ↔ g(, , 0) where , ∈ {1, 2, · · · , }
The same relation holds between predicate f(, , ) and . The only diference is that the domain of variable is {1, 2, · · · , }.
The variables we adopted to solve the problem have two types: • node that describes a node of the graph. Given an × boolean matrix, we will have exactly nodes with labels 1, 2, · · · , . The mapping from nodes to the variables is straightforward: node describes the variable —the variable that will have to match . • step, which describes the labelling of the edges.
Notice that we encoded this solution as a satisfiability problem. We provide the model with a candidate number of CNOT gates , and it tries to compute a graph with exactly edges. Therefore, the domain of the step variable is 1, 2, · · · , . The predicate describing an edge is: which holds if and only if the edge at step goes from node to node . Of course, we fixed all the constraints to make sure that for each step there exists exactly one edge with label .
For what concerns the val of a node, we introduced the predicate edge(, , ) value(, , ) 1 4 where , are nodes and is a step.
value(, , ) holds if and only if ∈ val ( ). We then encoded the update of value using the recursive definition introduced above.
We used the predicate value to check the final solution of the model at the -th step. For all , ∈ {1, 2, · · · , } the following must hold: g(, , 1) ↔ value(, , ) g(, , 0) ↔ ¬value(, , ) Forcing the model to search for graphs that satisfy the total behaviour imposed by .
Something similar has been done for the constraint on , with the only diference that can match the val of a node at any time. Hence, for all there must exists a ≤ and a such that for all ∈ {1, 2, · · · , }:
f(, , 1) ↔ value(, , ) f(, , 0) ↔ ¬value(, , ) 4.2. Symmetry Breaking symmetries in this problem play a key role to obtain good running times. Because of the model we proposed, symmetries are strictly related to connected components of the resulting graph. Take as an example the following matrix: The minimum number of CNOT required for this matrix is 3. Using the graph model, one possible solution is the one shown in Figure 3
Nevertheless, the only true constraint that must be satisfied, is that the edge between 1 and 2 must have a label smaller than the one of the edge between 2 and 3. Hence, the labelling (1, 2, 1), (2, 3, 3), (4, 5, 2) is correct too. This is clearly an example of symmetry that has to be broken. In particular, it concerns edges in diferent connected components.
In order to break this kind of symmetry, we forced the model to avoid leaving holes in the labelling in a single connected components. Suppose we have two connected components 1 and 2. And let , be the minimum and the maximum edge label in . Then it must be true that all the labels between and belong to .
This kind of constraints avoid any kind of symmetry between connected components with the same size. In case that 1 and 2 contains the same number of edges, let 1, 2 be the minimum edge labels of 1 and 2, respectively. Let be the source node of the edge with label 1 and be the source node of the edge with label 2. Then it must be true that 1 < 2 → < . Coping with symmetries introduced in diferent connected components clearly reduces the search space for the ASP solver. Nevertheless, symmetries in the same connected component also have to be taken into account.
In the same connected component, we want to find which pairs of edges can be swapped without modifying the solution’s correctness. Hence, we want to find pairs of edges ⟨, ℎ⟩ such that if we switch label between edge and edge ℎ the computed value function is unchanged.
To do so, we supposed to generate all the candidate swaps of the form ⟨, ℎ⟩, with < ℎ to avoid duplicate pairs. Then, we introduced a predicate fake_value(, , , , ) which has to be interpreted as a fake version of value in case that the swap ⟨, ℎ⟩ was performed. Hence, fake_value(, , , , ) holds if and only if ∈ val ( ) with edges and ℎ swapped.
The update of such predicate follows the rules of val, taking care of swapping source and destination of edges and ℎ. Clearly we are not interested in computing fake_value for all the time slots, but just for the between and ℎ. In fact, it is easy to see that if the behaviour is preserved in the time range , + 1, · · · , ℎ, the same will hold also for steps after time ℎ.
A candidate swap ⟨, ℎ⟩ is considered a valid swap if the following holds: ∀, ∈ {1, 2, · · · , }, ∀ ∈ {, + 1, · · · , } fake_value(, , , , ) ↔ value(, , )
Once valid swaps have been identified, we can use them as symmetry breakers.In particular, we split symmetries in 3 cases: • A valid swap ⟨, ℎ⟩ between edges of the form (, , ), (, , ). Then it must be true that < . • A valid swap ⟨, ℎ⟩ between edges of the form (, , ), (, , ). Then it must be true that < . • A valid swap ⟨, ℎ⟩ between edges of the form (, , ), (, , ). Then it must be true that < .
Roughly speaking, we fixed a unique choice for the swappable edges depending on their sources / destinations.
In the previous model, the graph had no constraint in its structure. Hence, it could contain cycles that makes the detection of swappable edges harder than expected.
On top of that, a graph with exactly one edge per time step, did not exploit the possibility of doing parallel CNOTs. For example, two CNOTs that share neither the control nor the target, can eventually be done in the same time step, since they do not interfere with each other.
For this reason, we decided to translate our general graph model into a DAG based one. The leaves of the DAG represent the problem variables. Hence, we will have leaves labelled 1, 2, · · · , . A CNOT with control and target is represented by a node with two incoming edges. One edge comes from the closer node labelled . The other from the closer node labelled . The generic structure of a node is depicted in Figure 4.
The DAG structure induces a layering of the nodes. Leafs are at layer 0. A node at layer , can only have incoming edges from nodes in smaller layers. One layer can contain more than a single node. Nevertheless, any layer can contain at most one node labelled , for any ∈ {1, 2, · · · , }.
The generated DAG , with the minimum number of node is the following: 1 2 3 2 3 where blue nodes are in layer 0, the green node composes layer 1, and layer 2 is composed by the single orange node. The circuit induced by applies CNOT(1, 2) followed by CNOT(2, 3).
As for the case with the model of Section 4, we must ensure that the DAG we build induces a circuit that implements . Given a DAG , the circuit it induces can be found through a visit from layer 1 up to layer exploiting the following rule: each internal node describes a CNOT gate and all the gates at layer must be executed before the gates at layer + 1, for all ∈ {1, 2, · · · , }.
Each layer of this model can be interpreted as the aggregation of more time steps from the general graph model.
In order to ensure that the circuit induced actually implements , we use the notion of Value from the previous section, tweaked for the layered DAG case.
The function Val is now defined in terms of layer: given a layer and variable , its value is described by Val(). The recursive definition of Val remains unchanged.
Hence, the correctness of the generated DAG is checked by imposing that in the last layer the following holds:
Val() = 5.1. Encoding in clingo We encoded all the above properties in clingo. We adopted the node type as for the graph encoding. We translated the step variables into layer variables.
Inner nodes of the graph are described by a predicate of the form xor_node(, , ) which has to be interpreted as follows: at layer , there is a node labelled which is the result of the XOR between and — CNOT( , ). Given a variable and a layer , we imposed that a single xor_node with target can exist at layer . Roughly speaking, xor_node is the equivalent of the edge in the graph case.
The predicate Value is handled in the same way as for the graph case. The only edit required is to interpret time steps in terms of layers.
Once Value is defined, also the final constraints on and are defined as in case of generic graph encoding.
In this model, we found much less symmetries than in the one from Section 4. The only one we could actually came up with is the following. Suppose xor_node(, , ) and xor_node(, , ) holds with < . Moreover, suppose all the variables edited between layer and layer are diferent from , and . Then it is true that CNOT( , ) at layer and CNOT( , ) at layer can be swapped, preserving the circuit overall behaviour.
In case that pairs of nodes of this kind were found in the solution, we forced the model the have the CNOT with the smaller target, at the lower layer. Formally speaking, if xor_node(, , ) and xor_node(, , ) can be swapped, then it must hold that < → < .
We tested the proposed models with the following procedure. For each ∈ {4, 5, 6, 7, 8} we generated 10 diferent random tests. For each test we created an × matrix, representing a linear reversible function, that will serve as — in the quantum case, is the number of qubits, that evolve through 2 × 2 unitary matrices. Moreover, for each test, we picked a number between 1 and , that will be the number of diferent we give as input to each test. We then run the two diferent models with an iterative procedure that works as follow. Let , {} be the input for the current test case. We initialized a counter to 1. We then run the graph model with input , {} and , to see if the problem was solvable in steps. If true, then we stored the running time and move to next sample. Otherwise, we increased and queried the model again. Notice that, by Theorem 1, will at most be 2.
For what concerns the DAG model, we applied the same procedure but expecting a diferent result from the model: the DAG model uses as number of layers, and then it minimizes the number of CNOT within the layers. Hence, when the model is satisfiable, we also have the computing time to get the optimal result for the given .
In Table 1 we report the obtained results for the graph method, while in Table 2 the results with the DAG approach.
In both tables, the first column is the quantity , the number of qubits. The second one is the average running time (in seconds) in the 10 tests. For each test, the time we measured is the overall time for the iterative procedure to find the solution, and not only the time for the satisfiable instance — even if we noticed that the unsatisfiability is found in less than 0.01 seconds in most of the cases. The tests have been run in a 2021 MacBookPro, with a 2 GHz Intel Core i5 quad-core CPU and 16GB of LPDDR4X Ram.
We can see from Table 1 and Table 2 that the DAG model is faster than the graph one. The generic graph model becomes useless with sizes bigger than 6. On the other hand, the DAG model is promising even if the running time is doubling every time the size increases. We tried to compare our results with the one presented in [8], but their procedure contains parts the we got for granted. For example, they start from an actual circuit, they extract the phase polynomial decomposition and just then try to minimize the circuit. In our case, we focused in the minimization part to see if we could somehow inject our solution into their algorithm. Since they tested their method with 6 × 6 matrices with running times of order of hundreds of seconds (in average), we are pretty confident that our DAG method would bring a significant speed up in the overall process.
In this paper we tackled the problem of minimizing the number of CNOT gates in a Quantum Circuits. We solved the problem with two diferent ASP models. The results we obtained show that the generic graph model is not very useful. On the other hand, the second DAG approach is promising. Further improvements are possible. For example, the search for the first for which the problem is satisfiable can be done through a binary search instead of trying all possible ’s. Deep investigations should be carried out also about the efectiveness of constraint programming in solving the same problem we tackled with ASP.
Despite that, it seems that Answer Set Programming can be fruitfully applied to the synthesis problem of quantum circuits in general, and not only in the CNOT case. Moreover, the solutions to this problem and solutions to problems such as the minimization of the number of T gates, paves down the road to the idea that the synthesis problem is not a monolith. Fast and not optimal techniques may be adopted to obtain a first and rough synthesis of some unitary . Starting from such synthesis, algorithms can be applied to systematically minimize parts of the circuits to obtain a reduction that is close to the optimal one. In order to benchmark the results of such approach, a great amount of test cases can be found in [17, 18]. [8] G. Meuli, M. Soeken, G. D. Micheli, Sat-based {CNOT, T} quantum circuit synthesis, in:
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