Methodology of FPGA Implementation and Performance Evaluation of Polar Coding for 5G Communications

Abstract

This article is devoted to the study of noise immunity of an infocommunication system with Polar Coding (P-C). The results of evaluating the performance of the Successive Cancellation (S-C) decoder are presented. The main contribution of this paper is the result of the compromise between high latency and Field Programmable Gate Array (FPGA) resources to implement a P-C decoder for 5G communications. The stages of channel polarization, the mathematical description of P-C, and the features of their description in binary channels are presented separately. This is achieved by the method of mathematical modeling of information and statistical characteristics of P-C for different code configurations. To check the correctness of the decisions made, a comparative description of the advantages and disadvantages of P-C decoding algorithms is given. The specifics of the FPGA implementation of the S-C algorithm have been studied. Based on the results of the experiment, the noise immunity of the P-C channel was assessed when changing the length of the code block, adding Cyclic Redundancy Check (CRC), and reversing bits at different code rates. It is expected that the results will be useful in optimizing the design process of real P-C circuits.

Keywords

• 1 5G
• FPGA
• polar codes
• decoding
• SNR

1. Introduction

Providing tasks related to the transmission of information in mobile telecommunications is certainly accompanied by a variety of error scenarios [ 1–3 ]. Among the main factors in the occurrence of errors, emphasis should be placed on random noise, as well as the imperfection of devices, which distorts streaming data on the receiving side. In such situations, where the concept of the receiver correcting such errors without additional information from the transmitter is involved, the forward error Correction (FEC) Format Is Implemented [ 4 ].

When implementing 5G NR technology [ 5– 7 ], the solution to the above problems is carried out by implementing the physical layer channel coding format through the integration of P-C and QCLDPC codes [ 8–10 ]. In general, 5G implementation contains the concept of increasing capacity for the eMBB deployment scenario—mobile communications; URLLC— ultra-reliable communication with minimal latency and mMTC—machine-type mass communications. This broad palette of 5G [ 11 ] implementations places a demand on channel encoders/decoders to support a variety of code lengths for both user and control data, including robust implementation of automatic repeat request (HARD) data.

Analysis of reliable P-C application scenarios allows us to confidently assert that such codes can increase communication throughput and, importantly, are characterized by simplified encoding/decoding procedures. In this case, you should pay attention to the S-C algorithm [ 12 ], which, due to its satisfactory complexity, has shown its effectiveness in real applications. Another important property of this algorithm is that it creates wide possibilities in the context of improving hardware architecture. We must emphasize that for P-C the compromise between high latency and FPGA resources is a problem area for reliable decoder implementations in the task of ensuring high throughput of information channels [ 13, 14 ].

A significant part of the available literature does not take into account the specifics of codes for 5G scenarios, as well as the process of encoding them, taking into account their further widespread use in the design of encoding circuits using FPGAs. The work [ 15 ] proposes a concept for implementing performance enhancement by introducing Polar Code Modulation with Physical Network Coding (PM-PNC) over Two-Way Relay Channels (TWRC). The article [ 16 ] focuses on describing a proposed method for building a Multi-Kernel (MK) P-C for 5G, based on large kernels of the same size to improve the quality of error correction. The paper [ 17 ] proposes a new coding scheme for 5G and P-C MIMOOFDM systems to improve the efficiency of channel error correction. The use of Convolutional Neural Networks (CNN) technology along with the use of P-C was proposed, which resulted in a significant increase in the reliability of the circuits. The proposed work [ 18 ] compares LDPC and P-C for robust implementations of 5G NR-URLLC channel coding schemes. An assessment of P-C performance for the described scenarios is given. Reasonable and balanced recommendations for the design and practical application of polar codes are reflected in several current publications [ 19–22 ].

Before formulating the problem statement for the research presented in the article, we will touch upon certain aspects of P-C. We emphasize that P-C is a family of Error Correction Codes (ECC), which are capable of achieving the throughput of memoryless symmetric channels. Such codes, with sufficient correction capacity, can satisfy the requirements for high-quality error correction for current block lengths and reliable decoding algorithms. It is these key factors that determine the intensive use of such codes in 5G applications.

Analysis of the principles of P-C decoding allows us to give such a characteristic to decoding algorithms. In the case of SC, an alternating bit evaluation of the message from 1 to N is implemented based on the format of the decision procedure. Therefore, it is important to note that the asymptotic performance of the S-C generally corresponds to the channel capacity, although in the case of finite code lengths, it is not always satisfactory. In this context, S-CL (successive cancellation list) decoding minimizes errors [ 23 ]. Note that practical schemes for using P-C can be implemented in a concatenated format with other codes, in particular CRC [ 12 ]. We also have to decouple the recursive P-C decoding scheme using Bhattacharyya Parameters (BP) [ 24 ]. Analysis of the above-described works of leading authors allows us to formulate the main issues that are addressed in the article. Thus, the complexity of the code determines the amount of energy consumed by the decoder, the amount of memory used, latency, and the overall computing power. Channel coding uses a set of operations on a data stream aimed at error correction. In such a context, to improve coding performance, it is necessary to synthesize highly productive code for efficient channel error localization. It is also important to solve the problem of synthesizing a decoding scheme with minimal cost, satisfactory encoding rate, and computational complexity.

The proposed work contains an addition to the works of the authors described above regarding the study of a communication system with an S-C decoder on an FPGA. Using MATLAB tools, the effectiveness of the proposed FPGA solutions was studied and the decoding noise immunity was assessed.

2. Channel Polarization and Polar

Encoder

From the point of view of designing P-C using FPGAs, it is quite important to maintain a balance between the delay value and the available matrix resources, which will directly affect the increase in the performance of a high-throughput decoder.

The general form of description of the P-C code word is х, implemented by representing the code length as N=2n and by K as the number of information bits. In addition, frozen bits in the form N-K are described. where = ⋅ 2⊗ is the representation of the generator matrix; BN is the form of the degree. permutation matrix, 2

⊗ is the n-th Kronecker = ⋅ , 2 = | 1 1 0 1

|,

Formula 3 represents the generator matrix for

N = 8.

Thus, the encoding scheme equivalent to the generator matrix is shown in × log2 0,5[ ( |0)+ ( |1)] ( | )

( ) = ∑

√ ( |0) ( |1), where

( | ) we denote the transition probabilities between output y and input x. (1) (2) (3) (4) (5)

It should be noted that the parameters used act as measures of rate and degree of reliability. So, by I(W) we mean the highest rate while ensuring reliable communication through W. Then Z(W) is interpreted as the upper limit on the probability of error in the case of a maximum likelihood decision. We emphasize that in this case Z(W) and I(W) belong to the values [ 0, 1 ]. An example of the action of a binary channel with erasure (B-EC) on a sequence of bits is shown in Fig. 2. Channel capacity I(W)≈1 in the case of Z(W)≈0, and I(W)≈0 in the case of Z(W)≈1 is described by formulas 6 and 7 [26].

(a) (b) on a sequence of (a) input and (b) output bits An example of channel capacity calculation for N = 8 is shown in Fig. 3. We used the following indicators for calculation: • Code length N = 8. • Code rate R = 0.5. • Number of information bits K = N*R = 4. • Number of frozen bits F = N-K = 4. • Positional configuration of information bits Ai∊ (5,3,2,1). • Positional configuration of the bits subjected to freezing A∊ (8,7,6,4).

Therefore, before transmitting the sequences, the indices of the ascending-sorted data sequence are divided into two sets. Thus, in this design, the first set is formed by indices of data transmitted in the absence of interference in the channel. While the second set covers known indices that are frozen and transmitted over noisy channels. Binary Symmetrical Channel (B-SC) and B-EC refer to symmetrical channels. The polarization operation can then be interpreted as the formation of N independent copies of a given BDMC channel W of another set of N channels { ( ): 1 ≤ ≤ } exhibiting the effect of polarization in such an interpretation that when N becomes large, the symmetric terms of the capacity ( ( )) are directed to 0 or 1 for all indices (see Fig. 4a). This operation consists of a channel combining step and a channel splitting step. In Fig. 4a we present the effect of channel polarization for conditions when W enters the B-EC with probability ε=0.5. Fig. 4a shows that ( ( )) tends to be close to 0 for small i and 1 for large i (is the node number, Fig. 4b) The binary tree formed by channel polarization is shown in Fig. 4b. An initial tree node is connected to channel W. Such a node W forms a top path W2(1) and a bottom path W2(2) that is connected to two nodes at level 1. The path W2(1) in turn generates branches of W4(1) and W4(2) so on. Path W2(i) is located at level n of the tree at node number i, counting from above.

Let’s analyze Fig. 4a. By the concept under consideration, the upper limit of BP corresponds to the state of the channel with the highest noise level, while the lower limit characterizes the state of the minimum noise. Consequently, the ideal state is determined by the discontinuity area in the BP extrema. At the transmitter side, K information bits are inserted into the noiseless channels, and N-K frozen bits are inserted into the corresponding pure noise channels to create an input vector 1 to be transmitted by the W channel. We use the BP parameter as a measure of reliability. Then such a parameter sets the upper limit on the probability of decision error for the maximum probability in the case of a transmission channel of a binary configuration.

3. Polar Decoder Concept

The basic polar decoding algorithm is already mentioned in the S-C article. There are also known decoding algorithms with higher performance for relatively short codewords but with greater complexity, such as the S-CL algorithm, the successive cancellation list decoding algorithm using CRC (CA-S-CL) [ 7 ], and the Belief Propagation (PB) algorithm [ 8 ]. The PB algorithm is well known for its application in LDPC decoding [ 7 ], in which soft messages are exchanged between nodes. In addition, the S-LC method stores a list of solutions and selects the best solution using sorting. Both have better performance, especially since the SLC algorithm provides the best BER gain for P-C with short block lengths. We will focus on the S-C decoding algorithm for FPGA implementation due to its satisfactory complexity.

Fig. 5 shows the FPGA implementation of the S-C decoder.

Each decoding stage is made up of N/2 nodes of type f and g (see Fig. 5), which are connected in a structure conceptually similar to a Fast Fourier Transform (FFT) butterfly. Nodes implement basic Likelihood Functions (LLR) like: ( , ) = 2 ℎ [ ℎ (2) ⋅ ℎ ( )], 2 ( ̂ , , ) = (1 − 2 ̂ ) + , Estimated values are calculated as follows: ̂ = { 0,

Pr( | ̂0−1, = 0) Pr( | ̂0−1, = 1)

≥ 1 1, otherwise

Equation (8) can be replaced by the minimum sum approximation, which is described by the expression: (6) (7) (8) (9) ( , ) = min(| |, | |), where a, b is the LLR. This approximation is typical for calculating the control node for the LDPC code [ 9 ]. The node g implementing (7) is a conditional addition/subtraction conditional on the value of the decision bit ̂ , where ̂ is the bit representing the partial sum modulo 2 of the previously calculated bits. The rule for calculating partial sums of ̂ is based on a structure that copies the corresponding P-S. Inside the Flow Data Graph (FDG) decoder there is an integrated FDG encoder. Then the partial sum ̂ for node, g1,2 is equal to ̂2 ⊗ ̂3, and the corresponding partial sum g3,4 is equal to ̂6. This means that to update node g, its output must determine ̂6. Then for hard messages, we get the following rule:

This approximation is used to calculate the control node. The S-C decoding algorithm is implemented by solving the following problems. In the first stage, the LLR (12) is determined and a hard decision is made. In the next, second stage, solutions are recursively propagated from the current nodes to the corresponding previous stage.

Thus, the end of the decoding process is the selection of the codeword with the most reliable path. In general, one can point to the improved performance of SCL compared to SC. This is especially noticeable at low noise levels and low LLR values. However, the SCL algorithm is more complex than the SC algorithm and, in addition, the decoder has an increased delay compared to the decoder implemented in the article using the SC algorithm.

Conducting a brief digest of P-C decoding algorithms, we emphasize that the CA-SCL algorithm [27] is an improved SCL algorithm for medium and short-length code structures. We emphasize that CRC is a frequency structure used to localize errors in several information transmission schemes. In this case, the K-bit encoder input block contains a structure of k information bits and an m-bit CRC sequence. CA-SCL-based decoding then performs a CRC check to reliably determine the codeword. This design is characterized by increased productivity.

It is necessary to mention the design of the BP decoder described by Arikan [26]. The structure of FDG here is similar to SC. However, in this case, the transfer of hard decisions is replaced with BP by estimates between check nodes and variable nodes. In this case, you can get a performance gain compared to SC, but using the concept of parallelism is quite problematic. Consequently, the BP decoder has increased complexity and limited throughput compared to the SC implementation

4. Development of a Low

Complexity Decoder

The graph configuration (Fig. 5) during S-C decoding is formed by 2n trees in binary form [28, 29]. To optimally use the resources of the FPGA circuit, one tree was built in binary form with the option of having custom nodes.

This architectural design of the P-C decoder was based on the use of the same pair of LLRs for a pair of nodes of type f and g. This approach allows you to concentrate nodes of type f and g in one processor unit. As noted above, one evaluation tree of a binary design was used—ûi (8). In this configuration, we received processing a

decoder units, and formed

from here the

LLR 2n-1 is estimated by

making a hard decision. In addition, the set of bit decisions used for the g nodes in the processing units is concentrated in memory for current use.

Let’s consider an eight-point P-C model based on the formation of two combinational decoders with N=4. This format is used to implement the parallel computing structure, and the generated graph for N = 8 is used to generate the input data of combinational decoders. The calculation of node g is implemented by supplying the output of the encoder with correctly identified bits and using the output of the decoder to make decisions at node g in the next stage. In the structure of the binary tree for the S-C decoder, when some of the blocks are inactive, an updated set of LLR channels is added.

To implement a node of type f, in the minimum sum (min-sum) approximation, the circuit includes a component that solves the ABC function to calculate the absolute value of the output. A comparator circuit is used to identify the minimum value. The circuit includes two multiplexers, where the first determines the minimum code value and generates the comparator output signal. Then the output of this multiplexer and its additional code are transmitted to the input of the second multiplexer in Fig. 6а.

The output signal of the XOR element generates a multiplexer selection signal. We calculate the min-sum using the following form:

The node function is formed by conditional depends on addition/subtraction, which the bit value ûs at the corresponding point in the decoder functional graph. Depending on the value, “a” is selected in one of the warehouses, or the additional code “a” is selected (Fig. 6b). This component implements the adder. Node g is defined by the following expression: ( ̂ , , ) = (1 − 2 ̂ ) + , (13) = ∗ min( ( ) ∗ ( ),   ( ) ( )). g

(12) (a) (b) the absolute value, CS is the compare and select, MUX is the multiplexer, and (b) g: SUM is the adder

5. Experimental Studies of the

Decoder

We conducted the research by implementing the communication system in MATLAB, Fig. 7.

To implement the P-C encoder and decoder, we selected the FPGA System-on-Chip (SoC) Intel DE10-Standard Development Kit. The Cortex-A9 processor has two integrated cores with programmable logic. The Cyclone V SE 5CSXFC6D6F31C6N SoC integrates an ARMbased Hard Processor System (HPS), consisting of a processor, peripherals, and memory interfaces coupled to an FPGA fabric. To ensure the tasks of transmitting information in a communication system via PC, we supplemented the structure of the encoded message with a CRC. The main purpose of adding redundancy is to increase noise immunity. Fig. 8 shows the general shape of the resulting frame and the shape of the generator polynomial: Using the above expression, the following bit sequence is formed: CRC-11 = [1 1 1 0 0 0 1 0 0 0 0 1]; CRC is effective as an external error detection code. In the case when the code length m does not agree with the length of the encoded frame (2log(M)), it is necessary to use the rate matching procedure by puncturing in N-M positions, with a total codeword length of N.

The next step is to carry out digital phase modulation and transmit the signals into the channel. The following operations are performed in the receiver: demodulation; rate restoration when the encoded sequence size (N) is updated, in particular by the number of punctured positions (P) of the codeword and is sent to the decoder; polar decoding to restore the transmitted message (described above in the article); redundancy implemented in the form of CRC is removed.

Fig. 9a shows the results of a study of the number of bit errors from the signal-to-noise ratio (SNR) for a communication system with BPSK modulation and different code block lengths.

There is no bit reversal, a CRC of 11 bits is connected. For a P-C with block length M = 32 and code rate R = 1/2, the number of informative bits taking into account CRC: K = 16. The number of encoded bits at the output of the P-C encoder is n = 32. In this case, there is no puncturing of P-C positions for rate matching [30]. (b) Figure 9: Dependence of BER on Eb/N0 for a communication system (a) With different code block lengths: 1 is the 32 bits; 2 is the 64 bits; 3 is the 128 bits; 4 is the 256 bits; 5 is the 512 bits; 5 is the 1024 bit; (b) With CRC and bit reversal Fig. 9b shows the results of a study of BER versus SNR [31] for a communication system with CRC and bit reversal.

From the results obtained, we can conclude that with an increase in the size of the data block (codeword) from 64 bits to 1024 bits, the noise immunity of the communication system increases by 1 dB.

From the results obtained, we can conclude that the presence of bit reversal accelerates the BER attenuation by 0.2 dB. Connecting CRC increases noise immunity by 0.5 dB.

In Figs. 10a and 10b we present the results of a study of the number of BER from the SNR for a communication system [32] with different exclusion list sizes (L) and different code rates, respectively. (b) Figure 10: Dependence of BER on Eb/N0 for a communication system (a) With different decoder list sizes lengths: 1 is the no list; 2 is the L = 1; 3 is the L = 2; 4 is the L = 4; 5 is the L = 8; 6 is the L = 16; 7 is the L = 32; (b) With different code rates: 1 is the R = 1/5; 2 is the R = 1/3; 3 is the R = 2/5; 4 is the R = 1/2; 5 is the R = 2/3; 6 is the R = 3/4; 7 is the R = 5/6; 8 is the R = 8/9 For modeling, the length of the code word was M = 4000, the length of the code word at the output of the encoder N = 4096, and the number of punctured bits P = 96.

From the obtained dependencies we can conclude that the SLC decoder makes it possible to increase the noise immunity of the communication system: even the list size L = 2 increases the noise immunity by 0.7 dB compared to the classic SL decoder. Further increasing the list size does not provide a significant performance improvement: increasing the list size from L = 2 to L = 32 increases noise immunity by 0.8 dB, but adds significant latency. Increasing the code rate has a greater impact on the bit error rate: increasing the code rate from 1/5 to 8/9 requires a 10 dB increase in the signal-to-noise ratio, but allows a 4.5 times higher data rate.

6. Conclusion

A study of the P-C communication system was carried out. The encoder, P-C decoder, and the principles of channel polarization are considered. The effect of the B-EC channel on a sequence of bits is analyzed. The capacity I(W) of each virtual polarized channel and the principles of dividing these channels into “bad” and “good” by BP value are determined.

A study of the number of bit errors from the signal-to-noise ratio was carried out for a communication system with BPSK modulation and different code block lengths, cyclic redundancy code and bit reversal, different sequential exclusion list sizes, and different code rates. From the results obtained, we can conclude that with an increase in the size of the data block (codeword) from 64 bits to 1024 bits, the noise immunity of the communication system increases by 1 dB. The presence of bit reversal accelerates the BER attenuation by 0.2 dB. Connecting CRC increases noise immunity by 0.5 dB.

Using an SLC decoder with a list size of L = 2 increases the noise immunity of the communication system by 0.7 dB compared to the classic SLC decoder. Further increasing the list size L = 32 increases noise immunity by 0.8 dB, but adds a significant delay. Increasing the code rate has a greater impact on the bit error rate: increasing the code rate from 1/5 to 8/9 requires an increase in the SNR by 10 dB, but allows you to increase the data transmission rate by 4.5 times.

References

[1] V. Astapenya , et al., Last Mile Technique for Wireless Delivery System using an Accelerating Lens , in: 2020 IEEE International Conference on Problems of Infocommunications. Science and Technology ( 2020 ). doi: 10 .1109/ picst51311. 2020 . 9467886 .

[2] V. Astapenya , V. Sokolov , D. Ageyev , Experimental Evaluation of an Accelerating Lens on Spatial Field Structure and Frequency Spectrum , in: IEEE Ukrainian Microwave Week ( 2020 ) 203 - 206 . doi: 10 .1109/ukrmw49653. 2020 . 9252755 .

[3] V. Astapenya , et al., Analysis of Ways and Methods of Increasing the Availability of Information in Distributed Information Systems , in: 2021 IEEE 8th International Conference on Problems of Infocommunications, Science and Technology ( 2021 ). doi: 10 .1109/ picst54195. 2021 . 9772161 .

[4] J. Bae , et al., An Overview of Channel Coding for 5G NR Cellular Communications , APSIPA Transactions on Signal and Information Processing , 8 ( 1 ) ( 2019 ). doi: 10 .1017/ATSIP. 2019 . 10 .

[5] A. Ghosh , et al., 5G Evolution: A View on 5G Cellular Technology Beyond 3GPP Release 15, IEEE Access 7 ( 2019 ) 127639 - 127651 . doi: 10 .1109/ACCESS. 2019 . 2939938 .

[6] I. Pyatin , et al., Implementation and Analysis of 5G Network Identification Operations at Low Signal-to-Noise Ratio, TELKOMNIKA (Telecommun . Comput. Electron. Control) 21 ( 3 ) ( 2023 ) 496 - 505 . doi: 10 .12928/telkomnika. v21i3. 22893 .

[7] J. Boiko , I. Pyatin , O. Eromenko , Analysis of Signal Synchronization Conditions in 5G Mobile Information Technologies, IEEE 16th International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering ( 2022 ). doi: 10.1109/ TCSET55632 . 2022 . 9766899 .

[8] B.-S. Su , C.-H. Lee , T.-D. Chiueh , A 58 .6/91.3 pJ/b Dual- Mode BeliefPropagation Decoder for LDPC and Polar Codes in the 5G Communications Standard , IEEE Solid-State Circuits Letters 5 ( 2022 ) 98 - 101 . doi: 10 .1109/LSSC. 2022 . 3167423 .

[9] J. Boiko , et al., Evaluation of the Capabilities of LDPC Codes for Network Applications in the 802.11ax Standard, IoT Based Control Networks and Intelligent Systems, IoT Based Control Netw . Intel. Syst. LNNS 789 ( 2024 ) 369 - 383 . doi: 10 .1007/ 978 -981-99-6586- 1_ 25 .

[10] J. Boiko , I. Pyatin , O. Eromenko , Simulation of the Transport Channel with Polar Codes for the 5G Mobile Communication , International Conference on Problems of Infocommunications. Science and Technology ( 2020 ) 182 - 186 . doi: 10 .1109/PICST51 311. 2020 . 9468013 .

[11] M. Morocho-Cayamcela , H. Lee , W. Lim , Machine Learning for 5G/B5G Mobile and Wireless Communications: Potential , Limitations, and Future Directions, IEEE Access 7 ( 2019 ) 137184 - 137206 . doi: 10 .1109/ACCESS. 2019 . 2942390 .

[12] H. Kim , H. Lee , H. Park , Distributed CRC Scheme for Low-Complexity Successive Cancellation Flip Decoding of Polar Codes, ICT Express 8(3) ( 2022 ) 409 - 413 . doi: 10 .1016/j.icte. 2021 . 10 .005.

[13] Z. Hu , et al., Development and Operation Analysis of Spectrum Monitoring Subsystem 2 . 4 - 2 .5 GHz Range, DataCentric Business and Applications 48 ( 2020 ) 675 - 709 . doi: 10 .1007/978-3- 030 -43070-2_ 29

[14] I. Bogachuk , V. Sokolov , V. Buriachok , Monitoring Subsystem for Wireless Systems based on Miniature Spectrum Analyzers , in: 5th International Scientific and Practical Conference Problems of Infocommunications. Science and Technology ( 2018 ) 581 - 585 . doi: 10 .1109/INFOCOMMST. 2018 . 8632151 .

[15] Z. Xie , et al., Polar Coded Modulation Operated with Physical Network Coding , IEEE Signal Processing Letters 28 ( 2021 ) 997 - 1001 . doi: 10 .1109/LSP. 2021 . 3078291 .

[16] C. Xia , C.-Y. Tsui, Y. Fan , Construction of Multi-Kernel Polar Codes with Kernel Substitution , IEEE Wireless Communications Letters 9 ( 11 ) ( 2020 ) [26] E. Arikan , Channel Polarization: A 1879-1883 . doi: 10 .1109/LWC. 2020 . Method for Constructing Capacity3006759 . Achieving Codes for Symmetric Binary-

[17] M. Meenalakshmi , S. Chaturvedi , Input Memoryless Channels, IEEE V. Dwivedi , Enhancing Channel Transactions on Information Theory Estimation Accuracy in Polar-Coded 55 ( 7 ) ( 2009 ) 3051 - 3073 . doi: MIMO-OFDM systems via CNN with 5G 10 .1109/TIT. 2009 . 2021379 . channel models, AEU - Int. J. Electron. [27] D. Tian , at al., Efficient Protection of Commun . 173 ( 2024 ) 155016 . doi: Polar Decoders Against Single Event 10 .1016/j.aeue. 2023 . 155016 . Upsets (SEUs) on User Memories ,

[18] A. Sharma , M. Salim , Performance Microelectron . Reliab . 149 ( 2023 ). doi: Evaluation of Polar Code for 10 .1016/j.microrel. 2023 . 115234 . Ultrareliable Low Latency Applications [28] W. Tan , ET AL., Area-Efficient Pipelined of 5G New Radio, Optical and Wireless VLSI Architecture for Polar Decoder , Technologies, LNEE 546 ( 2019 ) 261 - IEEE Computer Society Annual 270. doi: 10 .1007/ 978 -981-13-6159- Symposium on VLSI ( 2020 ) 352 - 357 . 3_28. doi: 10 .1109/ISVLSI49217. 2020 . 00071 .

[19] P. Chen , B. Bai , X. Ma , Nonbinary Polar [29] B. Bakkas , et al., Enhancing PAPR in Coding with Low Decoding Latency and OFDM System Using Polar Codes and μ- Complexity , J. Inf . Intel. 1 ( 1 ) ( 2023 ) 36 - Law Companding with Adaptive 53 . doi: 10 .1016/j.jiixd. 2022 . 10 .002. Modulation and Coding Rates , 6th

[20] O. Babalola , V. Balyan , Constant Weight International Conference on Advanced Polar Coded Orthogonal Space-Time Communication Technologies and Block Codes for Dimmable Indoor Networking ( 2023 ) 1 - 6 . doi: 10 .1109/ MIMO-VLC Systems , IEEE CommNet60167. 2023 . 10365278 . Communications Letters 26 ( 10 ) ( 2022 ) [30] А. Semenko , et al., Features of Creating 2395-2399 . doi: 10 .1109/LCOMM. 2022 . Based on Chaos Pseudo-Random 3193974 . Sequences , 14th International Conference

[21] M.-C. Chiu , Analysis and Design of Polar- on Advanced Trends in Radioelectronics, Coded Modulation , IEEE Transactions on Telecommunications and Computer Communications 70 ( 3 ) ( 2022 ) 1508 - Engineering ( 2018 ) 1087 - 1090 . doi: 1521. doi: 10 .1109/TCOMM. 2022 . 10 .1109/TCSET. 2018 . 8336383 . 3142280. [31] J. Boiko , et al., Method of the Adaptive

[22] O. Gazi , Polar Codes, Springer Topics in Decoding of Self-Orthogonal Codes in Signal Processing ( 2019 ). doi: Telecommunication, Indonesian J. Electr . 10 .1007/ 978 -981-13-0737-9. Eng. Comput. Sci . 19 ( 3 ) ( 2020 ) 1287 -

[23] C. Miao , Z. Shuang , Z. Shengmei , Multiple 1296. doi: 10 .11591/ijeecs.v19. i3 . pp CRC-aided Variable Successive 1287 - 1296 . Cancellation List Decoder of Polar Codes, [32] N. Vinogradov , et al., Development of the J. China Univ. Posts Telecommun . 24 ( 2 ) Method to Control Telecommunication ( 2017 ) 83 - 88 . doi: 10 .1016/S1005- Network Congestion Based on a Neural 8885 ( 17 ) 60202 - 4 . Model, Eastern-European J . Enterp.

[24] I. Baidari , N. Honnikoll , Bhattacharyya Technol. 2 ( 9 ) ( 2019 ) 67 - 73 . doi: Distance Based Concept Drift Detection 10 .15587/ 1729 - 4061 . 2019 . 164087 . Method for Evolving Data Stream, Expert Syst . Appl . 183 ( 2021 ) 115303 . doi: 10 .1016/j.eswa. 2021 . 115303 .

[25] H. Ochiai , P. Mitran , H. Poor, CapacityApproaching Polar Codes with Long Codewords and Successive Cancellation Decoding Based on Improved Gaussian Approximation , IEEE Transactions on Communications 69 ( 1 ) ( 2021 ) 31 - 43 . doi: 10 .1109/TCOMM. 2020 . 3030057 .