Methodology of FPGA Implementation and Performance Evaluation of Polar Coding for 5G Communications Juliy Boiko1, Volodymyr Druzhynin2, Serhii Buchyk2, Ilya Pyatin3, and Andrii Kulko4 1 Khmelnytskyi National University, 11 Instytuts’ka str., Khmelnytskyi, 29016, Ukraine 2 Taras Shevchenko National University of Kyiv, 60 Volodymyrska str., Kyiv, 01033, Ukraine 3 Khmelnytskyi Polytechnic Professional College by Lviv Polytechnic National University, 10 Zarichanska str., Khmelnytskyi, 29019, Ukraine 4 Military Institute of Taras Shevchenko National University of Kyiv, 60 Volodymyrska str., Kyiv, 01033, Ukraine Abstract This article is devoted to the study of noise immunity of an infocommunication system with Polar Coding (P-C). The results of evaluating the performance of the Successive Cancellation (S-C) decoder are presented. The main contribution of this paper is the result of the compromise between high latency and Field Programmable Gate Array (FPGA) resources to implement a P-C decoder for 5G communications. The stages of channel polarization, the mathematical description of P-C, and the features of their description in binary channels are presented separately. This is achieved by the method of mathematical modeling of information and statistical characteristics of P-C for different code configurations. To check the correctness of the decisions made, a comparative description of the advantages and disadvantages of P-C decoding algorithms is given. The specifics of the FPGA implementation of the S-C algorithm have been studied. Based on the results of the experiment, the noise immunity of the P-C channel was assessed when changing the length of the code block, adding Cyclic Redundancy Check (CRC), and reversing bits at different code rates. It is expected that the results will be useful in optimizing the design process of real P-C circuits. Keywords 1 5G, FPGA, polar codes, decoding, SNR. 1. Introduction carried out by implementing the physical layer channel coding format through the integration Providing tasks related to the transmission of of P-C and QCLDPC codes [8–10]. In general, 5G information in mobile telecommunications is implementation contains the concept of certainly accompanied by a variety of error increasing capacity for the eMBB deployment scenario—mobile communications; URLLC— scenarios [1–3]. Among the main factors in the ultra-reliable communication with minimal occurrence of errors, emphasis should be placed latency and mMTC—machine-type mass on random noise, as well as the imperfection of communications. This broad palette of 5G [11] devices, which distorts streaming data on the implementations places a demand on channel receiving side. In such situations, where the encoders/decoders to support a variety of concept of the receiver correcting such errors code lengths for both user and control data, without additional information from the including robust implementation of automatic transmitter is involved, the forward error repeat request (HARD) data. Correction (FEC) Format Is Implemented [4]. Analysis of reliable P-C application scenarios When implementing 5G NR technology [5– allows us to confidently assert that such codes 7], the solution to the above problems is CPITS-2024: Cybersecurity Providing in Information and Telecommunication Systems, February 28, 2024, Kyiv, Ukraine EMAIL: boiko_julius@ukr.net (J. Boiko); v_druzhinin@ukr.net (V. Druzhynin); buchyk@knu.ua (S. Buchyk); ilkhmel@ukr.net (I. Pyatin); kulko.andrii@gmail.com (A. Kulko) ORCID: 0000-0003-0603-7827 (J. Boiko); 0000-0002-5340-6237 (V. Druzhynin); 0000-0003-0892-3494 (S. Buchyk); 0000-0003-1898- 6755 (I. Pyatin); 0009-0006-1185-0774 (A. Kulko) ©️ 2024 Copyright for this paper by its authors. Use permitted under Creative Commons License Attribution 4.0 International (CC BY 4.0). CEUR Workshop Proceedings (CEUR-WS.org) CEUR ceur-ws.org Workshop ISSN 1613-0073 Proceedings 15 can increase communication throughput and, algorithms. It is these key factors that importantly, are characterized by simplified determine the intensive use of such codes in 5G encoding/decoding procedures. In this case, applications. you should pay attention to the S-C algorithm Analysis of the principles of P-C decoding [12], which, due to its satisfactory complexity, allows us to give such a characteristic to has shown its effectiveness in real applications. decoding algorithms. In the case of SC, an Another important property of this algorithm alternating bit evaluation of the message from is that it creates wide possibilities in the 1 to N is implemented based on the format of context of improving hardware architecture. We the decision procedure. Therefore, it is must emphasize that for P-C the compromise important to note that the asymptotic between high latency and FPGA resources is a performance of the S-C generally corresponds problem area for reliable decoder to the channel capacity, although in the case of implementations in the task of ensuring high finite code lengths, it is not always satisfactory. throughput of information channels [13, 14]. In this context, S-CL (successive cancellation A significant part of the available literature list) decoding minimizes errors [23]. Note that does not take into account the specifics of practical schemes for using P-C can be codes for 5G scenarios, as well as the process implemented in a concatenated format with of encoding them, taking into account their other codes, in particular CRC [12]. We also further widespread use in the design of have to decouple the recursive P-C decoding encoding circuits using FPGAs. The work [15] scheme using Bhattacharyya Parameters (BP) proposes a concept for implementing [24]. Analysis of the above-described works of performance enhancement by introducing leading authors allows us to formulate the Polar Code Modulation with Physical Network main issues that are addressed in the article. Coding (PM-PNC) over Two-Way Relay Thus, the complexity of the code determines Channels (TWRC). The article [16] focuses on the amount of energy consumed by the describing a proposed method for building a decoder, the amount of memory used, latency, Multi-Kernel (MK) P-C for 5G, based on large and the overall computing power. Channel kernels of the same size to improve the quality coding uses a set of operations on a data of error correction. The paper [17] proposes a stream aimed at error correction. In such a new coding scheme for 5G and P-C MIMO- context, to improve coding performance, it is OFDM systems to improve the efficiency of necessary to synthesize highly productive code channel error correction. The use of for efficient channel error localization. It is also Convolutional Neural Networks (CNN) important to solve the problem of synthesizing technology along with the use of P-C was a decoding scheme with minimal cost, proposed, which resulted in a significant satisfactory encoding rate, and computational increase in the reliability of the circuits. The complexity. proposed work [18] compares LDPC and P-C The proposed work contains an addition to for robust implementations of 5G NR-URLLC the works of the authors described above channel coding schemes. An assessment of P-C regarding the study of a communication performance for the described scenarios is system with an S-C decoder on an FPGA. Using given. Reasonable and balanced recom- MATLAB tools, the effectiveness of the mendations for the design and practical proposed FPGA solutions was studied and the application of polar codes are reflected in decoding noise immunity was assessed. several current publications [19–22]. Before formulating the problem statement 2. Channel Polarization and Polar for the research presented in the article, we will touch upon certain aspects of P-C. We Encoder emphasize that P-C is a family of Error Correction Codes (ECC), which are capable of From the point of view of designing P-C using achieving the throughput of memoryless FPGAs, it is quite important to maintain a symmetric channels. Such codes, with balance between the delay value and the sufficient correction capacity, can satisfy the available matrix resources, which will directly requirements for high-quality error correction affect the increase in the performance of a for current block lengths and reliable decoding high-throughput decoder. 16 The general form of description of the P-C code It should be noted that the parameters used word is х, implemented by representing the act as measures of rate and degree of code length as N=2n and by K as the number of reliability. So, by I(W) we mean the highest information bits. In addition, frozen bits in the rate while ensuring reliable communication form N-K are described. through W. Then Z(W) is interpreted as the 𝑥 = 𝑢 ⋅ 𝐺𝑁 , (1) upper limit on the probability of error in the case of a maximum likelihood decision. We where 𝐺𝑁 = 𝐵𝑁 ⋅ 𝐹2⊗𝑛 is the representation of emphasize that in this case Z(W) and I(W) the generator matrix; BN is the form of the belong to the values [0, 1]. An example of the permutation matrix, 𝐹2⊗𝑛 is the n-th Kronecker action of a binary channel with erasure (B-EC) degree. on a sequence of bits is shown in Fig. 2. 1 0 Channel capacity I(W)≈1 in the case of Z(W)≈0, 𝐹2 = | |, (2) 1 1 and I(W)≈0 in the case of Z(W)≈1 is described Formula 3 represents the generator matrix by formulas 6 and 7 [26]. for N = 8. Thus, the encoding scheme equivalent to the generator matrix is shown in Fig. 1 [10]. We used the concept of polarization for a Binary-Input Discrete Memoryless Channel (B-DMC) W and described the channel capacity I(W). 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 | 1 0 1 0 0 0 0 0| 1 1 1 1 0 0 0 0 𝐺8 = | |, (3) (a) 1 0 0 0 1 0 0 0 | 1 1 0 0 1 1 0 0| 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 (b) Figure 2: An example of the action of a B-EC on a sequence of (a) input and (b) output bits Figure 1: Polar encoder circuit for N = 8 An example of channel capacity calculation for N = 8 is shown in Fig. 3. We used the following We denote as 𝑊 𝑁 the channel corresponding indicators for calculation: to N using the W channel; thus 𝑊 𝑁 : 𝑋 𝑁 → 𝑌 𝑁 • Code length N = 8. from 𝑊 𝑁 (𝑦1𝑁 |𝑥1𝑁 ) = ∏𝑁𝑖=1 𝑊(𝑥𝑖 , 𝑦𝑖 ). In the • Code rate R = 0.5. description, parameters such as symmetric • Number of information bits K = N*R = 4. channel capacity [25] and the BP were used: • Number of frozen bits F = N-K = 4. 1 • Positional configuration of information 𝐼(𝑊) = ∑ ∑ 𝑊(𝑦|𝑥) × (4) 2 𝑦∈𝑌 𝑥∈𝑋 bits Ai∊ (5,3,2,1). • Positional configuration of the bits 𝑊(𝑦|𝑥) subjected to freezing A∊ (8,7,6,4). × log 2 𝑍(𝑊) = 0,5[𝑊(𝑦|0)+𝑊(𝑦|1)] Therefore, before transmitting the (5) ∑ √𝑊(𝑦|0)𝑊(𝑦|1), sequences, the indices of the ascending-sorted 𝑦∈𝑌 data sequence are divided into two sets. Thus, where 𝑊(𝑦|𝑥) we denote the transition in this design, the first set is formed by indices probabilities between output y and input x. 17 of data transmitted in the absence of Binary Symmetrical Channel (B-SC) and B-EC interference in the channel. While the second refer to symmetrical channels. The polarization set covers known indices that are frozen and operation can then be interpreted as the transmitted over noisy channels. formation of N independent copies of a given B- DMC channel W of another set of N channels (𝑖) {𝑊𝑁 : 1 ≤ 𝑖 ≤ 𝑁} exhibiting the effect of polarization in such an interpretation that when N becomes large, the symmetric terms of (𝑖) the capacity 𝐼 (𝑊𝑁 ) are directed to 0 or 1 for all indices (see Fig. 4a). This operation consists of a channel combining step and a channel splitting step. In Fig. 4a we present the effect of channel polarization for conditions when W enters the B-EC with probability ε=0.5. Fig. 4a (𝑖) shows that 𝐼 (𝑊𝑁 ) tends to be close to 0 for small i and 1 for large i (is the node number, Fig. Figure 3: Channel capacity calculation 4b) The binary tree formed by channel polarization is shown in Fig. 4b. (a) (b) Figure 4: Channel formation process (a) Channel polarization, (b) Binary tree formed by channel polarization An initial tree node is connected to channel W. the noiseless channels, and N-K frozen bits Such a node W forms a top path W2(1) and a are inserted into the corresponding pure bottom path W2(2) that is connected to two noise channels to create an input vector 𝑢1𝑁 nodes at level 1. The path W2(1) in turn to be transmitted by the W channel. We use generates branches of W4(1) and W4(2) so on. the BP parameter as a measure of Path W2(i) is located at level n of the tree at reliability. Then such a parameter sets the node number i, counting from above. upper limit on the probability of decision Let’s analyze Fig. 4a. By the concept error for the maximum probability in the under consideration, the upper limit of BP case of a transmission channel of a binary corresponds to the state of the channel configuration. with the highest noise level, while the lower limit characterizes the state of the minimum noise. Consequently, the ideal 3. Polar Decoder Concept state is determined by the discontinuity The basic polar decoding algorithm is already area in the BP extrema. At the transmitter mentioned in the S-C article. There are also side, K information bits are inserted into known decoding algorithms with higher 18 performance for relatively short codewords but node g implementing (7) is a conditional with greater complexity, such as the S-CL addition/subtraction conditional on the value algorithm, the successive cancellation list of the decision bit 𝑢̂𝑠 , where 𝑢̂𝑠 is the bit decoding algorithm using CRC (CA-S-CL) [7], and representing the partial sum modulo 2 of the the Belief Propagation (PB) algorithm [8]. The previously calculated bits. The rule for PB algorithm is well known for its application in calculating partial sums of 𝑢̂𝑠 is based on a LDPC decoding [7], in which soft messages are structure that copies the corresponding P-S. exchanged between nodes. In addition, the S-LC Inside the Flow Data Graph (FDG) decoder method stores a list of solutions and selects the there is an integrated FDG encoder. Then the best solution using sorting. Both have better partial sum 𝑢̂𝑠 for node, g1,2 is equal to 𝑢̂2 ⊗ performance, especially since the SLC algorithm 𝑢̂3 , and the corresponding partial sum g3,4 is provides the best BER gain for P-C with short equal to 𝑢̂6 . This means that to update node g, block lengths. We will focus on the S-C decoding its output must determine 𝑢̂6 . Then for hard algorithm for FPGA implementation due to its messages, we get the following rule: satisfactory complexity. 𝑗−1 𝑠 ⊕ 𝑠𝑖,𝑗+2𝑖−1 , | | mod2 = 0 Fig. 5 shows the FPGA implementation of 𝑠̂𝑖+1,𝑗 = { 𝑖,𝑗 2𝑖−1 (10) the S-C decoder. 𝑠𝑖,𝑗 , otherwise Each decoding stage is made up of N/2 This approximation is used to calculate the nodes of type f and g (see Fig. 5), which are control node. The S-C decoding algorithm is connected in a structure conceptually similar implemented by solving the following to a Fast Fourier Transform (FFT) butterfly. problems. In the first stage, the LLR (12) is Nodes implement basic Likelihood Functions determined and a hard decision is made. In the (LLR) like: next, second stage, solutions are recursively 𝑎 𝑏 (6) propagated from the current nodes to the 𝑓(𝑎, 𝑏) = 2𝑎𝑟𝑡ℎ [𝑡ℎ (2 ) ⋅ 𝑡ℎ (2)], corresponding previous stage. 𝑔(𝑢̂𝑠 , 𝑎, 𝑏) = (1 − 2𝑢̂𝑠 )𝑎 + 𝑏, (7) (11) 𝐿𝐿𝑅𝑖,𝑗 = Estimated values are calculated as follows: 𝑗−1 min(|𝐿𝐿𝑅𝑖+1,𝑗 |, |𝐿𝐿𝑅𝑖+1,𝑗+2𝑖−1 |), | | mod2 = 0 Pr(𝑦|𝑢̂0𝑖−1 , 𝑢𝑖 = 0) { 2𝑖−1 0, ≥1 (8) (1 − 2𝑠𝑖,𝑗−2𝑖−1 )𝐿𝐿𝑅𝑖+1,𝑗−2𝑖−1 + 𝐿𝐿𝑅𝑖+1,𝑗 , otherwise 𝑢̂𝑖 = { Pr(𝑦|𝑢̂0𝑖−1 , 𝑢𝑖 = 1) 1, otherwise Thus, the end of the decoding process is the Equation (8) can be replaced by the selection of the codeword with the most minimum sum approximation, which is reliable path. In general, one can point to the described by the expression: improved performance of SCL compared to SC. (9) This is especially noticeable at low noise levels 𝑓(𝑎, 𝑏) = min(|𝑎|, |𝑏|), and low LLR values. However, the SCL where a, b is the LLR. algorithm is more complex than the SC algorithm and, in addition, the decoder has an increased delay compared to the decoder implemented in the article using the SC algorithm. Conducting a brief digest of P-C decoding algorithms, we emphasize that the CA-SCL algorithm [27] is an improved SCL algorithm for medium and short-length code structures. We emphasize that CRC is a frequency structure used to localize errors in several information transmission schemes. In this Figure 5: P-C decoder code tree, N = 8 case, the K-bit encoder input block contains a structure of k information bits and an m-bit This approximation is typical for calculating CRC sequence. CA-SCL-based decoding then the control node for the LDPC code [9]. The performs a CRC check to reliably determine 19 the codeword. This design is characterized by ABC function to calculate the absolute value of increased productivity. the output. A comparator circuit is used to It is necessary to mention the design of the identify the minimum value. The circuit BP decoder described by Arikan [26]. The includes two multiplexers, where the first structure of FDG here is similar to SC. However, determines the minimum code value and in this case, the transfer of hard decisions is generates the comparator output signal. Then replaced with BP by estimates between check the output of this multiplexer and its nodes and variable nodes. In this case, you can additional code are transmitted to the input of get a performance gain compared to SC, but the second multiplexer in Fig. 6а. using the concept of parallelism is quite The output signal of the XOR element problematic. Consequently, the BP decoder has generates a multiplexer selection signal. We increased complexity and limited throughput calculate the min-sum using the following compared to the SC implementation form: 𝑜𝑢𝑡𝑝𝑢𝑡 4. Development of a Low = 𝑠𝑖𝑔𝑛(𝑙𝑎 ) ∗ 𝑠𝑖𝑔𝑛(𝑙𝑏 ) (12) Complexity Decoder ∗ min(𝑎𝑏𝑠(𝑙𝑎 ), 𝑎𝑏𝑠(𝑙𝑏 )). The node function g is formed by The graph configuration (Fig. 5) during S-C conditional addition/subtraction, which decoding is formed by 2n trees in binary form depends on the bit value ûs at the [28, 29]. To optimally use the resources of the corresponding point in the decoder functional FPGA circuit, one tree was built in binary form graph. Depending on the value, “a” is selected with the option of having custom nodes. in one of the warehouses, or the additional This architectural design of the P-C decoder code “a” is selected (Fig. 6b). This component was based on the use of the same pair of LLRs implements the adder. Node g is defined by the for a pair of nodes of type f and g. This following expression: approach allows you to concentrate nodes of 𝑔(𝑢̂𝑠 , 𝑎, 𝑏) = (1 − 2𝑢̂𝑠 )𝑎 + 𝑏, (13) type f and g in one processor unit. As noted above, one evaluation tree of a binary design was used—ûi (8). In this configuration, we received a decoder formed from 2n-1 processing units, and here the LLR is estimated by making a hard decision. In addition, the set of bit decisions used for the g nodes in the processing units is concentrated (a) in memory for current use. Let’s consider an eight-point P-C model based on the formation of two combinational decoders with N=4. This format is used to implement the parallel computing structure, (b) and the generated graph for N = 8 is used to Figure 6: Block diagram of nodes (a) f: ABS is generate the input data of combinational the absolute value, CS is the compare and decoders. The calculation of node g is select, MUX is the multiplexer, and (b) g: SUM implemented by supplying the output of the is the adder encoder with correctly identified bits and using the output of the decoder to make 5. Experimental Studies of the decisions at node g in the next stage. In the structure of the binary tree for the S-C Decoder decoder, when some of the blocks are inactive, an updated set of LLR channels is added. We conducted the research by implementing To implement a node of type f, in the the communication system in MATLAB, Fig. 7. minimum sum (min-sum) approximation, the To implement the P-C encoder and decoder, circuit includes a component that solves the we selected the FPGA System-on-Chip (SoC) 20 Intel DE10-Standard Development Kit. The ratio (SNR) for a communication system with Cortex-A9 processor has two integrated cores BPSK modulation and different code block with programmable logic. The Cyclone V SE lengths. 5CSXFC6D6F31C6N SoC integrates an ARM- There is no bit reversal, a CRC of 11 bits is based Hard Processor System (HPS), connected. For a P-C with block length M = 32 consisting of a processor, peripherals, and and code rate R = 1/2, the number of memory interfaces coupled to an FPGA fabric. informative bits taking into account CRC: K = 16. The number of encoded bits at the output of the P-C encoder is n = 32. In this case, there is no puncturing of P-C positions for rate matching [30]. Figure 7: Block diagram of the communication system with P-C To ensure the tasks of transmitting information in a communication system via P- C, we supplemented the structure of the encoded message with a CRC. The main purpose of adding redundancy is to increase noise immunity. Fig. 8 shows the general shape of the resulting frame and the shape of the generator polynomial: (a) 𝑔𝐶𝑅𝐶−11 (𝐷) = 𝐷11 + 𝐷10 + 𝐷 9 + (14) 𝐷 5 + 1, Figure 8: Appending CRC to data bits Using the above expression, the following bit sequence is formed: CRC-11 = [1 1 1 0 0 0 1 0 0 0 0 1]; CRC is effective as an external error detection code. In the case when the code length m does not agree with the length of the encoded frame (2log(M)), it is necessary to use the rate matching procedure by puncturing in N-M (b) positions, with a total codeword length of N. Figure 9: Dependence of BER on Eb/N0 for a The next step is to carry out digital phase communication system (a) With different code modulation and transmit the signals into the block lengths: 1 is the 32 bits; 2 is the 64 bits; channel. The following operations are 3 is the 128 bits; 4 is the 256 bits; 5 is the 512 performed in the receiver: demodulation; rate bits; 5 is the 1024 bit; (b) With CRC and bit restoration when the encoded sequence size reversal (N) is updated, in particular by the number of punctured positions (P) of the codeword and Fig. 9b shows the results of a study of BER is sent to the decoder; polar decoding to versus SNR [31] for a communication system restore the transmitted message (described with CRC and bit reversal. above in the article); redundancy From the results obtained, we can conclude implemented in the form of CRC is removed. that with an increase in the size of the data Fig. 9a shows the results of a study of the block (codeword) from 64 bits to 1024 bits, number of bit errors from the signal-to-noise the noise immunity of the communication system increases by 1 dB. 21 From the results obtained, we can conclude From the obtained dependencies we can that the presence of bit reversal accelerates conclude that the SLC decoder makes it the BER attenuation by 0.2 dB. Connecting CRC possible to increase the noise immunity of the increases noise immunity by 0.5 dB. communication system: even the list size L = 2 In Figs. 10a and 10b we present the results increases the noise immunity by 0.7 dB of a study of the number of BER from the SNR compared to the classic SL decoder. Further for a communication system [32] with increasing the list size does not provide a different exclusion list sizes (L) and different significant performance improvement: code rates, respectively. increasing the list size from L = 2 to L = 32 increases noise immunity by 0.8 dB, but adds significant latency. Increasing the code rate has a greater impact on the bit error rate: increasing the code rate from 1/5 to 8/9 requires a 10 dB increase in the signal-to-noise ratio, but allows a 4.5 times higher data rate. 6. Conclusion A study of the P-C communication system was carried out. The encoder, P-C decoder, and the principles of channel polarization are considered. The effect of the B-EC channel on a sequence of bits is analyzed. The capacity I(W) (a) of each virtual polarized channel and the principles of dividing these channels into “bad” and “good” by BP value are determined. A study of the number of bit errors from the signal-to-noise ratio was carried out for a communication system with BPSK modulation and different code block lengths, cyclic redundancy code and bit reversal, different sequential exclusion list sizes, and different code rates. From the results obtained, we can conclude that with an increase in the size of the data block (codeword) from 64 bits to 1024 bits, the noise immunity of the communication system increases by 1 dB. The (b) presence of bit reversal accelerates the BER Figure 10: Dependence of BER on Eb/N0 for a attenuation by 0.2 dB. Connecting CRC communication system (a) With different increases noise immunity by 0.5 dB. decoder list sizes lengths: 1 is the no list; 2 is Using an SLC decoder with a list size of L = 2 the L = 1; 3 is the L = 2; 4 is the L = 4; 5 is the increases the noise immunity of the L = 8; 6 is the L = 16; 7 is the L = 32; (b) With communication system by 0.7 dB compared to different code rates: 1 is the R = 1/5; 2 is the the classic SLC decoder. Further increasing the R = 1/3; 3 is the R = 2/5; 4 is the R = 1/2; 5 is list size L = 32 increases noise immunity by 0.8 the R = 2/3; 6 is the R = 3/4; 7 is the R = 5/6; 8 dB, but adds a significant delay. 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