Public-key cryptography solves the problem of key distribution, which is inherent in symmetric cryptography. However, there are problems associated with the high resource consumption of such crypto algorithms, which necessitates new methods to increase speed. The work is dedicated to the development of devices that perform modular squarebuilding, which is one of the basic operations in the implementation of public-key cryptosystems. The resolution of the implementation approach is being analyzed. The method is considered where the multiplication of a number by bits thereof is carried out starting from its senior digits. Two variants are proposed for the implementation of the central unit of the Partial Residue Shaper (PRF). The workability of the developed devices has been tested on the FPGA Artix-7 using the Verilog hardware description language.
Cryptographic security is one of the most reliable ways to address data security problems in computer systems and networks.
Cryptographic protection ensures the conversion of open text into micro text by encrypting source text using cryptographic algorithms [1, 2].
In modern cryptosystems, asymmetric
encryption [3] is widely used. This is because
public-key cryptosystems have potentially
high security as compared to symmetric (one
key) cryptosystems with a private key: there is
no need to transfer and authenticate secret
keys. A disadvantage of public-key
cryptosystems is their low speed, as encryption and
decryption procedures use much more
complex and cumbersome mathematical
calculations over large numbers [
Encryption can be done with software,
hardware, and hardware [
Hardware encryption has several
significant advantages over software
encryption [
systems guarantees its integrity. • Encryption and storage of keys is carried out in the cipher board itself and not in the computer’s RAM. • It is possible to create systems based on hardware ciphers to protect information from unauthorized access and to delimit access to a computer. • The use of paraphrase tires in the microprocessor architecture eliminates the threat of removing key information on electromagnetic radiation oscillations in the chains “Earth—Power” microcircuits, etc., arising during cryptographic transformations.
Define the basic operations over the numbers used in asymmetric cryptographic encryption algorithms. The construction of integers A to the power X modulo P (Ах mod P) is carried out by carrying out operations such as modular multiplication, and modular squaring. One approach to increasing the performance of public-key cryptosystems is to speed up the execution of these operations.
This work deals with the development of a modular square device. Various approaches to its development are analyzed. 2. Literature Review and Problem
Statement
In the first approach, a device for placing a
number A in a square is separately
synthesized, forming a 2N-bit number. Then,
with the individual device, the 2N-bit number
is given modulo. In the works [
With this approach, the complexity of
synthesized devices increases dramatically as
the number A decreases. The works [
In the works [
In the second approach, the elementary operations of squaring and modular multiplication are combined in one step. The squared number A in each step is multiplied by the polynomial members A = 0 + 121 … . + −22 −1 + −12 −1 from the lower or higher bits with the result of multiplication modulo P.
This article discusses a second approach— the development of a device for modular squaring of numbers, where multiplication is carried out from the higher bits of the factor. 3. Development of the Devices 3.1. Devices for Modularizing into a
Square Fig. 1 shows a functional modular squaring circuit where multiplication A begins with a higher bit— −1.
The device comprises RgA1 and RgA2 registers for receiving and storing the number A. RgA2 has a left-to-left shift circuit, RgP serves for storing the module P, RgR for storing the current residue values and the result of the operation. There are also Add1 binary and Partial Residue Shaper (PRF), Synchronization Block (BSIN), which contains a subtracting counter (Count), delay lines DL.1, DL.2, DL.3.
BSIN inputs are provided with Clock pulse signals, the binary N-1 shift number code.
Clock signals are emitted at BSIN outputs and are directed to the input of the moving RgA2.
Count = 0 BSIN generates the “End of operation” signal.
Fig. 2 shows the functional circuit of the PRF
partial residue shaper (1-variant), which
consists of two binary Add3 and Add2 and a
block of AND8-AND10 circuits, and a block of
OR1 circuits. Left-shifting ̅Р is applied to the
right inputs of Add3, and ̅Р is shifted to the
right inputs of Add2. The input of the lower bits
of adders is given a level of +1. On the left
inputs of Add1 the sum = 2 −1 + ∗ is
given from the outputs of the Add1 adder. In
PRF, the operation = . is executed
[
Furthermore, Add3 takes the value Sign3 = 0, which blocks the transfer to the output AND9 of the difference − Р from the outputs of Add2. With > 2 the signal on the symbol output of the value to the outputs AND8 and OR3. In of the Add2 Sign2 = 0, which blocks the this case, R = . transfer to the output of AND10 of the value . Let’s consider an example. А = 4310 =
With ˂2 , Sign3 = 1 and 2 = 1 allow the { 5 4 3 2 1 0 difference − from Add2 output to be 1 0 1 0 1 12 transmitted to AND9 outputs. Furthermore, = 5410: 2 = 10810 the Sign2 = 0 signal blocks the transmission of Calculation order = 432 54 is shown the value to the outputs of AND10. For < in Table 1. 2Р и < , the Sign2 = 1 signal is transmitted to the PRF output via the AND10 block of circuits.
Since the hardware cost of an N-bit binary adder is about 3 times that of an N-bit comparison circuit, it is advisable to construct a partial residue collector by replacing one binary adder with two comparison schemes.
For this reason, Fig. 3 shows the second variant of the PRF partial residue shaper functional scheme, which is based on one binary adder and two comparison schemes COMP-1 and COMP-2.
In this scheme, the value = 2 −1 + ∗ is given by the left inputs of the COMP-1 scheme, where it is compared to the value of 2P, and in the COMP-2 scheme the value of is compared to the value of P. If it is ≥ 2Р, then at the output of 2 COMP-1 the “1” signal is generated, which allows the 2̅Р value to pass to the right inputs of the Add2 adder. Since the value of is given to the left inputs, = + 2 ̅ + 1 is executed.
If 2 > ≥ conditions are met, then a signal “1” is formed at the output of the AND9 circuit, which allows passing the value Р̅. = + ̅ + 1 to the right inputs of Add2.
When < Р a single signal is generated at Fig. 3. Functional circuit of the partial residue output 1 of COMP-2, which allows the passage shaper (2—variant) Checking: = 432 = 1849 54 = 1849 − 1836 = 1310
In Fig. 4 a functional circuit of the device of modular number-squaring based on two Add1, Add2, and two PRF residue shapers (2— = = 43 = 86 = 107 = 106 0 = 0 1 = 1 54 = 4310 5 = 3210 2 = 2 3 = 3 4 = 4 = 5310 = 5210 = 147 − 2 = 147 − 108 = 3910 5 = 5
= 121 − 2 = 121 − 108 = 1310
variant) is shown, where on each clock number
A is multiplied by two higher bits of the RgA2
register, which reduces by half the number of
shifts of RgA2 [
The experimental research showed the correct functioning of the developed devices for modularizing numbers into a square. A singlestage synthesis of the modular squaring device is more efficient than a two-stage synthesis, which makes it possible to handle the required number of operand bits without complicating the structure and composition of the operating blocks.
Future research study is related to the practical implementation of the proposed devices in real cryptosystems to provide security and privacy at high speed.