Magnetic Resonance Fingerprinting (MRF) is a fast quantitative MR Imaging technique that provides multiparametric maps with a single acquisition. Neural networks (NNs) accelerate reconstruction but require significant resources for training. We propose an FPGA-based NN for real-time brain parameter reconstruction from MRF data. Training the NN takes an estimated 200 seconds, significantly faster than standard CPU-based training, which can be up to 250 times slower. This method could enable real-time brain analysis on mobile devices, revolutionising clinical decision-making and telemedicine.
supported by artificial intelligence (AI) in data analysis [
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The purpose of this work involves hardware programming for an FPGA-accelerated NN training algorithm for the reconstruction of MR parameters (T1 and T2) using clinical MRF. To test the ability to accelerate the training process on FPGA, the original NN must first be redesigned, i.e., simplified and quantized, to meet the available resources of the hardware accelerator. This would result in an important reduction in training time and power consumption.
The NN model by Barbieri et al. [
A low-level HDL design approach, in which every firmware component is written in VHDL, without
any high-level synthesis support, has been selected, ensuring full control and data protection through
an on-FPGA firewall security algorithm [
This function was generically implemented once and then used all the necessary times to cover all the node operations present in the NN. Proper functioning was verified by deploying 16 nodes in the FPGA and comparing their output with those of Python. Secondly, the backpropagation algorithm was implemented. As a starting point, the simple stochastic gradient descent was chosen, which describes how the parameters of the NN, i.e. weights and biases, are updated at each iteration during training, following Eq. (2).
Finally, an assessment was conducted to evaluate the resource requirements for node operations, backpropagation, and memory storage on the FPGA, involving the necessary LUTs, DSPs, and FFs.
design. In our scenario, based on the synthesis outcomes of a single node and the backpropagation
=1 = ( ∑ ⋅ + ) = ((w+1 ) +1 ) ∘ ′( )
ℒ w = −1 and ℒ = MAPE (%)
MPE (%) RMSE (ms) process, a clock frequency of 200 MHz is totally feasible, with the possibility of increasing it to 250 MHz. Based on the estimation of the required resources for executing all the necessary operations on the FPGA, the whole network and backpropagation algorithm cannot be implemented on the FPGA but, it is feasible to implement 16 nodes of the second layer on the FPGA, as well as the backpropagation between the layers containing 16 and 32 nodes. Thus, by iterating these two blocks multiple times in a semiparallelised way, all the operational requirements of the network can be covered.
To verify the correct implementation of the single node function in VHDL, the outputs produced on both the FPGA and in software were compared after providing identical inputs, weights, and biases. The comparison produced promising results, as there was no diference between the Python outputs and those of the FPGA, indicating that the mathematical operations were correctly translated into VHDL.
The estimate of the necessary FPGA resources was 145k LUTs, 5k DSPs, and 146k FFs. This implies that the entire NN and backpropagation use 8% of the available LUTs and 40% of the available DSPs, demonstrating that the algorithm’s implementation is entirely viable from the resource point of view. PCI Express technology was chosen to communicate from the PC’s CPU to the FPGA and back resulting in additional resources of 83k LUTs, 148kn FFs and 150 BRAMs, the internal RAM memories of the FPGA.
Finally, a fairly accurate estimate of the training time can be made. Each node needs 4 clock cycles to perform its operations. The 16 nodes implemented on the FPGA work in a semi-parallel way, resulting in 56 clock cycles required for all levels. Similarly, the single backpropagation module requires 3 clock cycles, iterating through the entire process for a total of 104 clock cycles. With a clock frequency of 200 MHz, the clock period is 5 ns, considering 250M training data the total training time results in: (5 ⋅ (250′000′000 ⋅ (56 + 104)))= 200 s (3)
This result highlights how the NN can be trained on FPGA in less than 5 minutes, which is 200 times faster than the corresponding training on CPU. The proposed method poses a big step in the direction of real-time and personalized healthcare, opening the possibility of having an integrated NN hardware accelerator for map reconstruction inside the MRI scanner.
The author would like to thank all the people who contributed to this work: Fabrizio Alfonsi (INFN Bologna), Camilla Marella (University of Bologna), Marco Barbieri (Stanford University), Alessandra Retico (INFN Pisa), Leonardo Brizi (University of Bologna), Alessandro Gabrielli (University & INFN Bologna), Claudia Testa (University & INFN Bologna).