Moving data processing closer to its source, known as edge computing, ofers significant advantages including reduced latency, bandwidth savings, and enhanced reliability. However, implementing complex algorithms on edge devices is challenging due to power and computational limitations. In this context, Spiking Neural Networks (SNNs) emerge as a promising solution due to their energy eficiency. This work presents a preliminary version of an accelerator for Spiking Neural Networks designed to be integrated into a System-on-Chip (SoC). The accelerator was developed using the open-source Process Design Kit (PDK) SKY130A and the open-source Electronic Design Automation (EDA) tool OpenLane. Preliminary results highlight the potential of SNNs for edge applications, as well as the advantages of using these new open-source tools, which reduce cost barriers and facilitate transparent information exchange.
In recent years, the deployment of artificial intelligence (AI) algorithms at the edge has gained significant traction, driven by the exponential growth of Cyber-Physical Systems (CPS) and Internet of Things (IoT) devices. Moving data processing as close as possible to the source ofers significant benefits, such as the ability to perform real-time processing, reduce latency, and improve overall system eficiency. However, implementing these algorithms on edge devices is challenging due to constraints related to energy consumption and computational power.
Spiking Neural Networks (SNNs) have emerged as a promising AI algorithm for edge applications due to their energy eficiency. Unlike traditional neural networks, SNNs mimic the brain’s spiking behavior, leading to lower power consumption and improved performance in event-driven scenarios. This makes SNNs particularly suitable for edge computing, where energy resources are constrained, and eficient processing is crucial.
These networks are ideally better performed on neuromorphic processors, which can fully exploit the sparsity of events and ofer remarkable eficiency. Neuromorphic hardware is designed to support the unique operational characteristics of SNNs, such as asynchronous processing and event-driven computation, resulting in significant energy savings and faster response times. However, the adoption of neuromorphic processors is still limited due to high costs and integration challenges with existing edge devices.
In light of these considerations, the objective of this work is to develop a low-power accelerator for SNNs to be integrated into a System on Chip (SoC) for edge applications.
Leveraging current trends, we have utilized an open-source Process Design Kit (PDK) and open-source Electronic Design Automation (EDA) tools to implement the system. This approach not only aligns with the growing emphasis on open-source solutions but also enhances the flexibility, accessibility, and cost-efectiveness of our design process.
The main findings of this study can be summarized as follows: • we present an SNN accelerator integrable into a SoC, such as the Efabless Caravel1; • we present an initial version of the accelerator layout, created using exclusively open-source tools; • we have demonstrated that the SNN accelerator is a viable solution for edge applications, achieving an energy consumption of 3.7 per inference at a frequency of 89 MHz.
The remainder of the paper is organized as follows: Section 2 provides a brief overview of related works, Section 3 provides an introduction to spiking neural networks, the architecture of the accelerator, and the RTL-GDSII flow. Finally, Section 4 discusses the obtained results, while Section 5 outlines future work, and Section 6 presents the conclusions.
Currently, several specialized neuromorphic processors are highly efective in executing SNNs. These
advanced processors, as detailed in [
More relevant to this work are the studies [
To the best of our knowledge, there are no works that describe accelerators for SNNs developed entirely using open-source tools. However, several studies have explored the potential of these emerging tools and demonstrated their capabilities in various applications.
The studies by [
Finally, the study in [10] represents the most complex project, utilizing OpenRoad [11] and Yosys [12] tools along with the open-source PDK IHP-SG13 to develop Basilisk, the first fully open-source, Linux-capable RISC-V SoC. Basilisk features a 64-bit RISC-V core, a fully digital HyperRAM DRAM controller, and a comprehensive set of I/O peripherals, including USB 1.1 and VGA. This work highlights the advantage ofered by open-source tools to better customize the provided scripts. by modifying the Yosys and OpenRoad scripts, we achieved better results compared to using the non-customized scripts, including higher system clock frequencies and reduced area occupancy.
Spiking neural networks are defined as the third generation of neural networks. What distinguishes them from other conventional neural networks is their use of a more realistic neuron model. Neurons 1https://caravel-harness.readthedocs.io/en/latest/ communicate with each other through binary signals known as spikes and maintain an internal state called membrane potential.
The neuron model used in this work is the Leaky Integrate and Fire (LIF) neuron, which is described by the following equation:
[] = [ − 1] + ∑︁ [] − [ − 1] [] = {︃1, if [] > 0, otherwise (1) where represents the neuron’s membrane potential, is the membrane potential decay rate, denotes the synaptic weights, indicates the input spikes, is the output spike, and represents the neuron’s threshold. When the potential exceeds the threshold value , a spike is generated and a reset mechanism is activated, subtracting the threshold value from the potential.
The communication through spikes makes these networks particularly interesting from an energy standpoint for several reasons. Spiking neural networks operate in an event-driven manner, where signals remain inactive for extended periods and only become active when spikes occur. This phenomenon, known as sparsity, allows the system to process information only when necessary, thus avoiding unnecessary operations and conserving energy during inactive periods. Additionally, since the inputs to these neurons are binary (0 or 1), the computational operations primarily involve simple accumulation rather than complex multiplications. This reduces the overall algorithmic complexity and leads to lower energy consumption compared to conventional neural networks, which rely heavily on multiplication operations. These characteristics make spiking neural networks highly eficient and well-suited for edge applications where energy eficiency is critical.
The proposed system is an accelerator for Spiking Neural Networks intended for integration into a
System-on-Chip (SoC). This version of the accelerator is a modified adaptation of the one described in
[
As the original design leveraged FPGA-specific components like configurable blocks of memory (BRAMs) and hard-wired Digital Signal Processor (DSP), several modifications were required to adapt the architecture to the PDK used. Modules previously implemented with DSPs were replaced by combinational logic, while blocks originally implemented with BRAMs were substituted with fourteen 4 Kbyte single-port SRAM memories 2 and flip-flops.
In particular, the weight memories were implemented using eight memories, while the spike memories were realized using flip-flops, as this approach proved more area-eficient due to the mismatch with the available memory blocks. In the FPGA, the BRAMs were dual-port, allowing simultaneous read and write operations. Therefore, the FIFOs for membrane potentials were implemented to support concurrent read and write access. However, since the available memories are now single-port, it was necessary to adapt the architecture by using two separate memories and a state machine. During each inference, one memory is used for reading and the other for writing, swapping roles in the subsequent inference. Finally, two memories were used to store the decay factors. Weights are stored in 8-bit integer format, membrane potentials in 32-bit format to avoid saturation, and decay factors in 14-bit format. The accelerator receives input spikes in groups of four, while the membrane voltages of the neurons in the final layer of the network are used as output.
The accelerator executes a network with four dense layers, using two layer hardware modules on which two layers are mapped each. Each module contains a memory that stores the synaptic weights, a FIFO where the neurons’ decay factors are saved, and a FIFO where the neurons’ membrane potentials are saved. Each layer also includes two stacks that dynamically address the active input synapses and two memories that store the generated spikes. Additionally, every layer contains a module that calculates
the synaptic current and a neuron module for updating the LIF neuron state.
The hardware layer module operates as follows: the module receives input spikes, grouped in sets of four, and stores them in the spike memory 0, keeping track of the addresses of the active groups in the spike stack 0. The addresses saved in stack 0 are used to access the weight memory, where the weights are also stored in groups of four and are summed based on the spike condition of the associated synapses stored in spike memory 0. The LIF modules update the potential of the neurons and generate the spikes for the next layer. The generated spikes are again grouped in sets of four and stored in spike memory 1, and the active addresses are saved in stack 1. This process is then repeated, and the generated outputs become the input for the next layer module.
SNN accelerator Layer module 0
Layer module 1 Input
Potentials Memory Decays Memory
Spike Memory 1
Spike Memory 0 Stack 0 Stack 1
LIF 4-way Synaptic adder
Weights Memory
Potentials Memory Decays Memory
Spike Memory 1
Spike Memory 0 Stack 0 Stack 1
LIF 4-way Synaptic adder
Weights Memory
Output
To develop the chip layout of the proposed system, the open-source OpenLANE flow [
The flow relies entirely on open-source tools: Yosys [ 12] for synthesis, OpenSTA 3 for static timing analysis, and OpenROAD [11] for floorplanning, placement, CTS, and routing. KLayout 4 generates the ifnal GDSII layout file, while Magic 5 and Netgen 6 are used for Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verification.
The tool is compatible with both A and B variants of the open-source SKY130 PDK, the C variant of the open-source GF180MCU PDK, and includes documentation for adding support for other PDKs, including proprietary ones. For this work, version A of the open-source SKY130 PDK was selected, to enable the integration of the system onto Caravel.
The flow is completely automated and requires only the RTL files describing the system and a configuration file, in either JSON or TCL format, which outlines the settings to follow.
The table 1 presents the main statistics of the chip. In the figure 2, the layout visualized with Klayout is shown on the left, while the placement density visualized through the OpenROAD graphical interface is shown on the right. The core area of the chip was chosen to meet the constraints imposed by the Caravel Harness and occupies 46% of the available area, leaving 5.7 mm² of space for additional modules. The system can operate at a maximum frequency of 89 MHz, dissipating a power of 54.3 mW at this frequency, as calculated using the OpenSTA tool.
Since the hardware can perform 4-synaptic additions per clock cycle, one inference can be executed every , expressed as
= sy4napse · (2) where synapse is the number of active synapses and is the clock period.
In the worst-case scenario, where all the synapses are active, is equal to 70 s and energy dissipated per inference is equal to 3.7 J.
A fundamental aspect of using spiking neural networks is the process of converting inputs from real values to spike trains. Conversely, the process of converting the output spikes from the network back into real values is equally important. In the proposed accelerator, it is assumed that the encoding phase has already been completed, with spikes being received directly as input, while the decoding phase is not necessary as the output is the membrane potential, which is already a real value. In the future, the goal is to add spike encoding and decoding modules to make the system as complete as possible. Various conversion algorithms have been proposed in the literature for the conversion task, including Ben’s Spiker [13], step-forward [14] or Pulse width modulated-Based [15], which are better suited depending on the use case. To accommodate diferent applications, the plan is to integrate an embedded FPGA (eFPGA) into the accelerator. This will allow for the mapping of various encoding and decoding algorithms, depending on the application, leveraging the flexibility of FPGA reconfigurability while maintaining the low power consumption of an ASIC. This integration will be facilitated by new open-source tools, including OpenFPGA [16] and FABulous [17], which enable the generation of RTL to describe the FPGA and provide the necessary tools to generate the bitstream for configuring them. Once the eFPGA is integrated into the system, the final goal will be to perform the tapeout of the chip.
In this work, we presented an accelerator for SNNs designed for integration into a SoC. An initial version of the accelerator layout was provided, created entirely using open-source tools and compatible with integration into the Caravel SoC. Additionally, the energy eficiency of the accelerator was demonstrated, with an energy consumption of 3.7 µJ per inference at a frequency of 89 MHz.
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