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  <front>
    <journal-meta>
      <journal-title-group>
        <journal-title>Scientific Reports</journal-title>
      </journal-title-group>
    </journal-meta>
    <article-meta>
      <article-id pub-id-type="doi">10.1038/s41598-024-84130-8</article-id>
      <title-group>
        <article-title>Detection for Safety-Critical RISC-V Automotive Systems</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <string-name>Elio Vinciguerra</string-name>
          <email>elio.vinciguerra@phd.unict.it</email>
          <xref ref-type="aff" rid="aff0">0</xref>
          <xref ref-type="aff" rid="aff1">1</xref>
          <xref ref-type="aff" rid="aff2">2</xref>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Maurizio Palesi</string-name>
          <email>maurizio.palesi@unict.it</email>
          <xref ref-type="aff" rid="aff0">0</xref>
          <xref ref-type="aff" rid="aff1">1</xref>
          <xref ref-type="aff" rid="aff2">2</xref>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Giuseppe Ascia</string-name>
          <email>giuseppe.ascia@unict.it</email>
          <xref ref-type="aff" rid="aff0">0</xref>
          <xref ref-type="aff" rid="aff1">1</xref>
          <xref ref-type="aff" rid="aff2">2</xref>
        </contrib>
        <aff id="aff0">
          <label>0</label>
          <institution>Anomaly detection</institution>
          ,
          <addr-line>Artificial Intelligence, gem5, RISC-V, Hardware Performance Counters</addr-line>
        </aff>
        <aff id="aff1">
          <label>1</label>
          <institution>CPSWS'25: CPS Summer School PhD Workshop</institution>
        </aff>
        <aff id="aff2">
          <label>2</label>
          <institution>University of Catania</institution>
          ,
          <addr-line>Catania</addr-line>
          ,
          <country country="IT">Italy</country>
        </aff>
      </contrib-group>
      <pub-date>
        <year>2025</year>
      </pub-date>
      <volume>15</volume>
      <issue>2025</issue>
      <fpage>693</fpage>
      <lpage>706</lpage>
      <abstract>
        <p>Modern automotive systems are evolving into complex cyber-physical platforms, where traditional fixed-policy fault recovery mechanisms prove insuficient against sophisticated faults and cyber-attacks. This work presents an anomaly detection framework for RISC-V-based automotive systems, combining Hardware Performance Counters (HPC) with additional hardware metrics to improve detection accuracy under realistic conditions. The methodology is validated by running FreeRTOS workloads on a full-system RISC-V architecture with controlled fault injection using the CHAOS framework. A comparative analysis of sequence-aware and classical machine learning models demonstrates that integrating temporal data significantly enhances detection, with the GRUAutoencoder showing the best trade-of between performance and computational eficiency for safety-critical scenarios.</p>
      </abstract>
    </article-meta>
  </front>
  <body>
    <sec id="sec-1">
      <title>1. Introduction</title>
      <sec id="sec-1-1">
        <title>CEUR</title>
      </sec>
      <sec id="sec-1-2">
        <title>Workshop</title>
        <p>ISSN1613-0073
c m
Fault Fault Fault Fault</p>
        <p>Checking Checking Checking Checking</p>
        <p>Check
su ive Period
ttaSnio Defetc
tu al
xeE Nor
Artificial Intelligence</p>
        <p>Detaelcetritoinngand
Application Execution (clock cycles)</p>
      </sec>
    </sec>
    <sec id="sec-2">
      <title>2. Proposed Methodology</title>
      <p>
        The framework logic has been presented and analyzed in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ]. At every Check Period (CP), the system
state is sent to a computing platform, which uses artificial intelligence models to analyze hardware
metrics in order to classify the execution status, as illustrated in Figure 1.
      </p>
      <sec id="sec-2-1">
        <title>2.1. FreeRTOS Configuration</title>
        <p>
          FreeRTOS is a lightweight, open-source real-time operating system kernel widely adopted in embedded
and automotive applications due to its minimal resource footprint and portability across heterogeneous
hardware platforms, including RISC-V. Through FreeRTOS, it becomes possible to analyze system
behavior in more realistically accurate environments, which is why it has been employed as the
operating system executing tasks for the purposes of this work. The selected tasks correspond to the
MiBench benchmarks [
          <xref ref-type="bibr" rid="ref6">6</xref>
          ] from the Automotive and Industrial Control suite, specifically BasicMath and
BitCount. The FreeRTOS application configured in this manner will be simulated in gem5 [
          <xref ref-type="bibr" rid="ref7">7</xref>
          ] to obtain
the hardware metrics necessary for this work.
        </p>
      </sec>
      <sec id="sec-2-2">
        <title>2.2. Hardware metrics</title>
        <p>
          In order to classify the execution status as normal or defective, this work employs HPC, following
established approaches in the literature [
          <xref ref-type="bibr" rid="ref10 ref11 ref8 ref9">8, 9, 10, 11</xref>
          ]. HPC are specialized registers that track various
microarchitectural events during program execution, providing low-overhead monitoring capabilities
for detecting anomalous behavior patterns. For the purposes of this work, a comprehensive set of
RISCV performance counters is monitored, including basic execution metrics (  ,  ,   ) and
specialized hardware performance events covering instruction execution patterns, memory subsystem
behavior, cache performance, and branch prediction accuracy (ℎ 4 − 5 , ℎ 7 −
15, ℎ 22 , ℎ 27 − 31 ). These counters provide detailed insights into arithmetic
operations, load/store instructions, cache misses, Translation Lookaside Bufer (TLB) performance, and
pipeline behavior. However, the exclusive use of HPC may not be suficient to fully characterize an
execution. To test the efectiveness of machine learning models, a secondary set of metrics is introduced,
representing diferent aspects of the system including cache hierarchy performance, memory controller
behavior, branch prediction statistics, instruction throughput, and overall system utilization patterns.
The secondary metrics that are most suitable for integration into the system have been extracted
through a comprehensive framework that combines four complementary feature selection methods via
an ensemble approach. This framework incorporates neural attention weights derived from custom
self-attention layers, permutation importance through systematic feature shufling, mutual information
for statistical feature-target dependencies, and cross-dataset stability via bootstrap sampling analysis.
The complete mechanism of this system will not be discussed in detail in this work; however, it is
RiscvO3CPU
dcache_port
icache_port
system_port
mem_cntrls
        </p>
        <p>port
SystemXBar membus
badaddr_responder</p>
        <p>
          pio
cpu_side_ports default mem_side_ports
inspired by the methodology presented in [
          <xref ref-type="bibr" rid="ref12">12</xref>
          ].
2.3. CHAOS
system
plic
pio
        </p>
        <p>HiFive platform
GenericRiscvPciHost RiscvRTC RiscvUart8250
pio int_pin pio</p>
        <p>pio
bridge
cpu_side_port mem_side_port
clint
int_pin</p>
        <p>
          IOXBar iobus
mem_side_ports
cpu_side_ports
The concrete evaluation of normal or defective execution classification necessitated the use of a fault
injector. The Controlled Hardware fAult injectOr System (CHAOS) [
          <xref ref-type="bibr" rid="ref13">13</xref>
          ] addresses this need by enabling,
through its modular structure, the modeling of faults in CPU registers, cache memory hierarchy, and
main memory. CHAOS is a fault injector specifically designed for gem5, and its distinctive feature lies
in its modular and open-source nature. The system is organized into three diferent modules, which
ofer the ability to inject faults into: CPU registers (CHAOSReg), cache hierarchy (CHAOSCache), and
main memory (CHAOSMem). All Instruction Set Architectures (ISAs) and CPU models supported by
gem5 are fully compatible with CHAOS. CHAOS provides comprehensive control over fault injection
parameters, encompassing fault type and injection methodology, fault occurrence frequency, and
temporal distribution patterns. This granular control enables the configuration of highly flexible fault
injection campaigns capable of emulating arbitrary fault scenarios and systematically analyzing their
consequential impact on system behavior and reliability characteristics.
        </p>
      </sec>
    </sec>
    <sec id="sec-3">
      <title>3. Experiments &amp; Results</title>
      <p>
        This section provides a comprehensive review of experiments designed to determine which machine
learning algorithm and hardware metrics set are most suitable for realistically accurate scenarios
compared to those presented in [
        <xref ref-type="bibr" rid="ref5">5</xref>
        ].
      </p>
      <sec id="sec-3-1">
        <title>3.1. Experiments Setup</title>
        <p>
          The simulated RISC-V system employs a FullSystem configuration based on the HiFive platform,
operating at 1 GHz with a three-level cache hierarchy: 16 KiB L1I, 64 KiB L1D, and 256 KiB L2, backed
by 2048 MiB of DDR4 DRAM. An out-of-order (O3) processor in RV64 mode executes the workload with
a CP interval of 1,000,000 clock cycles, whose selection rationale is detailed in [
          <xref ref-type="bibr" rid="ref5">5</xref>
          ]. Figure 2 illustrates
the complete architectural setup adopted for the gem5-based simulation.
        </p>
        <p>CHAOS has been configured to initiate fault injection at a randomly selected clock cycle at the
beginning of each simulation, with fault probabilities ranging from 1 × 10−1 to 1 × 10−8 and a random
number of bits to alter using a random fault mask.</p>
        <p>Furthermore, to diversify FreeRTOS executions and present results based on increasingly realistic
scenarios, the parameters of BasicMath and BitCount tasks have been randomized at compile time.
Each fault-free simulation operates with a distinct parameter set.</p>
      </sec>
      <sec id="sec-3-2">
        <title>3.2. Machine Learning Techniques</title>
        <p>The identification of the most efective machine learning approach for anomaly detection necessitated
an analysis across multiple algorithmic paradigms. Eight distinct methodologies were evaluated:
Isolation Forest, K-means clustering, K-nearest neighbors (KNN), Local Outlier Factor (LOF), Support
Accuracy and F1 Score of various Machine Learning Algorithms Using HPC Only.
reflects established practices within the field [</p>
        <p>
          <xref ref-type="bibr" rid="ref14">14, 15, 16, 17</xref>
          ], ensuring methodological alignment with
current research standards. Each algorithm was deployed in its one-class variant, a configuration
that enables comprehensive pattern recognition across varied operational conditions while facilitating
robust learning of nominal system behavior without requiring labeled anomalous examples during the
training phase.
        </p>
        <p>The experimental dataset comprised 500 normal execution traces complemented by 14,000
synthetically generated faulty instances. These defective samples were systematically created through
randomized fault injection across diferent temporal points and hardware abstraction layers within
the CHAOS framework, ensuring comprehensive fault space coverage. This unsupervised learning
approach allows the models to internalize the fundamental characteristics of correct system operation,
subsequently enabling detection of any deviation from expected behavior patterns. Consequently,
the trained models can identify novel anomalies without prior exposure to specific fault signatures,
demonstrating superior generalization capabilities compared to supervised approaches constrained by
predefined fault categories.
Each algorithm was evaluated in two distinct configurations: a sequenced (S) variant, where the input
consists of a temporal window of 14 consecutive multivariate HPC samples; and a non-sequenced (NS)
variant, where the input is limited to a single multivariate sample. Notably, certain models–such as
the LSTM-Autoencoder and GRU-Autoencoder–are inherently designed to process sequential data and
therefore cannot be applied in the non-sequenced setting. In addition, for each algorithm we analyzed
how detection accuracy varies depending on the specific architectural component afected by fault
injection. Overall, results indicate that, except for the LOF algorithm in its non-sequenced variant and
the MLP in its sequenced variant, most approaches achieve reasonably acceptable accuracy. However, it
is worth highlighting that none of the models shows satisfactory performance when faults are injected
into main memory, which remains the most challenging scenario.</p>
        <p>To enhance detection performance in scenarios where faults are injected into the main memory, an
additional set of hardware metrics–introduced in Section 2.2–has been integrated into the analysis. The
resulting performance improvements are reported in Table 2. The data demonstrate that incorporating
additional hardware metrics beyond HPC alone yields comparable average accuracies across nearly all
experimental classes, with the notable exception of the non-sequenced MLP, which exhibits significant
performance degradation. However, this mechanism enables improved accuracy for faults injected into
main memory, resulting in satisfactory solutions. Contrary to the results obtained using only HPC
(Table 1), the present analysis with an extended set of metrics (Table 2) reveals a marked diference
between sequenced and non-sequenced configurations. This divergence can be attributed to the intrinsic
characteristics of the algorithms employed. Traditional machine learning algorithms–Isolation Forest,
K-Means, KNN, LOF, SVM, and MLP–were originally designed for static data processing and lack
inherent mechanisms for handling temporal sequences. When the number of features per sequence is
increased, these algorithms exhibit performance degradation in processing sequential inputs, as they
are unable to efectively capture temporal dependencies in the data. Conversely, algorithms based on
recurrent neural networks–LSTM-Autoencoder and GRU-Autoencoder–are specifically designed for
temporal sequence processing and demonstrate greater robustness in handling extended sequential data.
Their architecture enables the retention and utilization of previous temporal information, resulting in
more stable performance regardless of the data presentation modality. Among the solutions that best
adapt to the scope of the present work from an accuracy perspective are the KNN algorithms (both
sequenced and non-sequenced variants), LOF (sequenced version), SVM (non-sequenced version), and
the GRU-Autoencoder.</p>
        <p>Given the stringent computational constraints inherent to automotive applications, the selection of
algorithmically eficient mechanisms becomes paramount. Consequently, the evaluation framework
must encompass not merely predictive accuracy but also the computational complexity profiles of
candidate algorithms to ensure real-time feasibility in resource-constrained environments. The complexity
analysis reveals distinct computational signatures: KNN operates with  ( ⋅ ) , complexity, where 
represents the dataset cardinality and  the feature dimensionality. LOF demonstrates quadratic scaling
at  ( 2 ⋅ ) , attributed to the intensive pairwise distance computations required for local density
estimation. In contrast, SVM exhibits  ( ⋅  ) complexity, with  denoting the support vector cardinality—a
parameter typically orders of magnitude smaller than the full dataset. The GRU-Autoencoder exhibits a
complexity of  ( ⋅ (ℎ 2 + ℎ ⋅ )) , where  represents the sequence length, ℎ denotes the hidden state
dimension, and  represents the input dimension. Given that in our case ℎ ≫  , this expression simplifies
to  ( ⋅ ℎ 2), since each GRU cell requires  (ℎ 2) operations for the hidden-to-hidden transformations at
each time step, and this quadratic term dominates the linear input-to-hidden term  (ℎ ⋅ ) .</p>
        <p>The GRU-Autoencoder is favored over traditional methods such as KNN, LOF, and SVM for sequential
temporal data due to its capability to capture temporal dependencies and evolutionary patterns that
these conventional approaches, which rely on static local density estimation or geometric separation
principles, are inherently unable to detect. While KNN and LOF operate under the assumption of
point independence with computational complexity directly proportional to dataset size, and SVM,
despite also assuming point independence, achieves inference complexity dependent on support vectors
rather than full dataset size, the GRU-Autoencoder demonstrates superior scalability by operating with
complexity dependent on sequence length and embedding dimensionality, thereby achieving enhanced
computational eficiency for inference on sequential data where temporal anomalies necessitate a
sequence-aware methodology rather than conventional point-wise data analysis.</p>
      </sec>
    </sec>
    <sec id="sec-4">
      <title>4. Conclusions</title>
      <p>This work has presented an adaptive anomaly detection framework for RISC-V-based automotive
systems, addressing the limitations of traditional fixed-policy fault recovery by exploiting both HPC and
complementary hardware metrics. Through realistic simulations using FreeRTOS workloads and
controlled fault injection, we demonstrated that sequential models—particularly the GRU-Autoencoder—can
efectively capture temporal execution patterns, improving detection accuracy even in challenging
scenarios like faults injected into main memory. While classical methods such as KNN, LOF, and SVM
remain competitive, our results show that sequence-aware approaches ofer a better balance between
accuracy and computational eficiency for safety-critical applications. As next steps, future work will
focus on integrating concrete fault mitigation and recovery strategies into the framework, moving from
pure detection to active resilience.</p>
      <p>Acknowledgments
This work has been (partially) supported by the Spoke 1 ”FutureHPC &amp; BigData” of the Italian Research
Center on High-Performance Computing, Big Data and Quantum Computing (ICSC) funded by MUR
Missione 4 - Next Generation EU (NGEU) and MUR PRIN COLTRANE-V E53D23008060006.</p>
    </sec>
    <sec id="sec-5">
      <title>Declaration on Generative AI</title>
      <p>During the preparation of this work, the author(s) used ChatGPT-4o in order to: Paraphrase and reword,
Grammar and spelling check. After using this tool/service, the author(s) reviewed and edited the content
as needed and take(s) full responsibility for the publication’s content.</p>
    </sec>
  </body>
  <back>
    <ref-list>
      <ref id="ref1">
        <mixed-citation>
          [1]
          <string-name>
            <given-names>S.</given-names>
            <surname>Kim</surname>
          </string-name>
          ,
          <string-name>
            <surname>K.-J. Park</surname>
            ,
            <given-names>C.</given-names>
          </string-name>
          <string-name>
            <surname>Lu</surname>
          </string-name>
          ,
          <article-title>A survey on network security for cyber-physical systems: From threats to resilient design</article-title>
          ,
          <source>IEEE Communications Surveys &amp; Tutorials</source>
          <volume>24</volume>
          (
          <year>2022</year>
          )
          <fpage>1534</fpage>
          -
          <lpage>1573</lpage>
          . doi:
          <volume>10</volume>
          .1109/COMST.
          <year>2022</year>
          .
          <volume>3187531</volume>
          .
        </mixed-citation>
      </ref>
      <ref id="ref2">
        <mixed-citation>
          [2]
          <string-name>
            <surname>SAE</surname>
          </string-name>
          ,
          <source>Automated vehicles: The role of iso 26262, in: The Role of ISO 26262</source>
          ,
          <year>2020</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref3">
        <mixed-citation>
          [3]
          <string-name>
            <given-names>International</given-names>
            <surname>Organization</surname>
          </string-name>
          for Standardization, ISO/FDIS 26262, ISO-26262
          <string-name>
            <surname>Road Vehicles - Functional Safety</surname>
          </string-name>
          , International Standard, International Organization for Standardization,
          <year>2011</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref4">
        <mixed-citation>
          [4]
          <string-name>
            <given-names>A.</given-names>
            <surname>Waterman</surname>
          </string-name>
          ,
          <string-name>
            <given-names>Y.</given-names>
            <surname>Lee</surname>
          </string-name>
          ,
          <string-name>
            <given-names>R.</given-names>
            <surname>Avizienis</surname>
          </string-name>
          ,
          <string-name>
            <given-names>H.</given-names>
            <surname>Cook</surname>
          </string-name>
          ,
          <string-name>
            <given-names>D.</given-names>
            <surname>Patterson</surname>
          </string-name>
          ,
          <string-name>
            <given-names>K.</given-names>
            <surname>Asanovic</surname>
          </string-name>
          ,
          <article-title>The risc-v instruction set</article-title>
          ,
          <source>in: 2013 IEEE Hot Chips 25 Symposium (HCS)</source>
          ,
          <year>2013</year>
          , pp.
          <fpage>1</fpage>
          -
          <lpage>1</lpage>
          . doi:
          <volume>10</volume>
          .1109/HOTCHIPS.
          <year>2013</year>
          .
          <volume>7478332</volume>
          .
        </mixed-citation>
      </ref>
      <ref id="ref5">
        <mixed-citation>
          [5]
          <string-name>
            <given-names>E.</given-names>
            <surname>Vinciguerra</surname>
          </string-name>
          , E. Russo,
          <string-name>
            <given-names>M.</given-names>
            <surname>Palesi</surname>
          </string-name>
          ,
          <string-name>
            <surname>G.</surname>
          </string-name>
          <article-title>Ascia, Data-driven simulation based fault detection in automotive risc-v applications</article-title>
          ,
          <source>in: 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)</source>
          ,
          <year>2024</year>
          , pp.
          <fpage>509</fpage>
          -
          <lpage>516</lpage>
          . doi:
          <volume>10</volume>
          .1109/
          <string-name>
            <surname>MCSoC64144</surname>
          </string-name>
          .
          <year>2024</year>
          .
          <volume>00089</volume>
          .
        </mixed-citation>
      </ref>
      <ref id="ref6">
        <mixed-citation>
          [6]
          <string-name>
            <given-names>M. R.</given-names>
            <surname>Guthaus</surname>
          </string-name>
          ,
          <string-name>
            <given-names>J. S.</given-names>
            <surname>Ringenberg</surname>
          </string-name>
          ,
          <string-name>
            <given-names>D.</given-names>
            <surname>Ernst</surname>
          </string-name>
          ,
          <string-name>
            <given-names>T. M.</given-names>
            <surname>Austin</surname>
          </string-name>
          , T. Mudge, R. B.
          <string-name>
            <surname>Brown</surname>
          </string-name>
          , Mibench:
          <article-title>A free, commercially representative embedded benchmark suite</article-title>
          ,
          <source>in: IEEE 4th Annual Workshop on Workload Characterization</source>
          , Austin, TX,
          <year>2001</year>
          .
        </mixed-citation>
      </ref>
      <ref id="ref7">
        <mixed-citation>
          [7]
          <string-name>
            <surname>J. L.-P.</surname>
          </string-name>
          et al.,
          <source>The gem5 simulator: Version 20.0+</source>
          ,
          <year>2020</year>
          . arXiv:
          <year>2007</year>
          .03152.
        </mixed-citation>
      </ref>
      <ref id="ref8">
        <mixed-citation>
          [8]
          <string-name>
            <given-names>P. M.</given-names>
            <surname>Anand</surname>
          </string-name>
          ,
          <string-name>
            <given-names>P. V. S.</given-names>
            <surname>Charan</surname>
          </string-name>
          ,
          <string-name>
            <given-names>S. K.</given-names>
            <surname>Shukla</surname>
          </string-name>
          ,
          <article-title>Hiper - early detection of a ransomware attack using hardware performance counters</article-title>
          ,
          <source>Digital Threats</source>
          <volume>4</volume>
          (
          <year>2023</year>
          ). URL: https://doi.org/10.1145/3608484. doi:
          <volume>10</volume>
          .1145/3608484.
        </mixed-citation>
      </ref>
      <ref id="ref9">
        <mixed-citation>
          [9]
          <string-name>
            <given-names>M.</given-names>
            <surname>El Bouazzati</surname>
          </string-name>
          ,
          <string-name>
            <given-names>P.</given-names>
            <surname>Tanguy</surname>
          </string-name>
          , G. Gogniat,
          <string-name>
            <given-names>R.</given-names>
            <surname>Tessier</surname>
          </string-name>
          ,
          <article-title>Diwall: A lightweight host intrusion detection system against jamming and packet injection attacks</article-title>
          ,
          <source>ACM Trans. Embed. Comput. Syst</source>
          . (
          <year>2025</year>
          ). URL: https://doi.org/10.1145/3711833. doi:
          <volume>10</volume>
          .1145/3711833, just Accepted.
        </mixed-citation>
      </ref>
      <ref id="ref10">
        <mixed-citation>
          [10]
          <string-name>
            <given-names>A.</given-names>
            <surname>Palumbo</surname>
          </string-name>
          ,
          <string-name>
            <given-names>R.</given-names>
            <surname>Salvador</surname>
          </string-name>
          ,
          <article-title>Leveraging gem5 for hardware trojan research: Simulation for machinelearning-based detection</article-title>
          ,
          <source>in: Proceedings of the 22nd ACM International Conference on Computing Frontiers: Workshops and Special Sessions</source>
          , CF '25 Companion, Association for Computing Machinery, New York, NY, USA,
          <year>2025</year>
          , p.
          <fpage>9</fpage>
          -
          <lpage>16</lpage>
          . URL: https://doi.org/10.1145/3706594.3728869. doi:
          <volume>10</volume>
          .1145/3706594.3728869.
        </mixed-citation>
      </ref>
      <ref id="ref11">
        <mixed-citation>
          [11]
          <string-name>
            <surname>A.-T. Le</surname>
            , T.-T. Hoang,
            <given-names>B.-A.</given-names>
          </string-name>
          <string-name>
            <surname>Dao</surname>
            ,
            <given-names>A.</given-names>
          </string-name>
          <string-name>
            <surname>Tsukamoto</surname>
            ,
            <given-names>K.</given-names>
          </string-name>
          <string-name>
            <surname>Suzaki</surname>
          </string-name>
          , C.
          <article-title>-K. Pham, A real-time cache side-channel attack detection system on risc-v out-of-order processor</article-title>
          ,
          <source>IEEE Access 9</source>
          (
          <year>2021</year>
          )
          <fpage>164597</fpage>
          -
          <lpage>164612</lpage>
          . doi:
          <volume>10</volume>
          .1109/ACCESS.
          <year>2021</year>
          .
          <volume>3134256</volume>
          .
        </mixed-citation>
      </ref>
      <ref id="ref12">
        <mixed-citation>
          [12]
          <string-name>
            <surname>K. K. Abrokwa</surname>
            ,
            <given-names>Q.</given-names>
          </string-name>
          <string-name>
            <surname>Jiang</surname>
            ,
            <given-names>Z.</given-names>
          </string-name>
          <string-name>
            <surname>Ma</surname>
            ,
            <given-names>Y. Zhang,</given-names>
          </string-name>
          <article-title>Explainable performance anomaly detection and rectification in sixth generation open radio access network based on contrastive and deep reinforcement learning</article-title>
          , Available at SSRN (
          <year>2024</year>
          ). URL: https://ssrn.com/abstract=5171031. doi:
          <volume>10</volume>
          .2139/ssrn.5171031.
        </mixed-citation>
      </ref>
      <ref id="ref13">
        <mixed-citation>
          [13]
          <string-name>
            <given-names>E.</given-names>
            <surname>Vinciguerra</surname>
          </string-name>
          , E. Russo,
          <string-name>
            <given-names>M.</given-names>
            <surname>Palesi</surname>
          </string-name>
          , Chaos, https://github.com/eliovinciguerra/CHAOS.git,
          <year>2024</year>
          . URL: https://github.com/eliovinciguerra/CHAOS.git.
        </mixed-citation>
      </ref>
      <ref id="ref14">
        <mixed-citation>
          [14]
          <string-name>
            <given-names>K.</given-names>
            <surname>Zhan</surname>
          </string-name>
          ,
          <string-name>
            <given-names>C.</given-names>
            <surname>Wang</surname>
          </string-name>
          ,
          <string-name>
            <given-names>X.</given-names>
            <surname>Zheng</surname>
          </string-name>
          , et al.,
          <article-title>Seq2seq-based gru autoencoder for anomaly detection and</article-title>
        </mixed-citation>
      </ref>
    </ref-list>
  </back>
</article>