{"labels":{"en":"Dataflow-based FPGA Accelerators Generation via MLIR and Multi-dataflow Composer tool"},"descriptions":{"en":"scientific paper published in CEUR-WS Volume 4106"},"claims":{"P31":"Q13442814","P1433":null,"P1476":{"text":"Dataflow-based FPGA Accelerators Generation via MLIR and Multi-dataflow Composer tool","language":"en"},"P407":"Q1860","P953":"https://ceur-ws.org/Vol-4106/short6.pdf","P50":[],"P2093":[{"value":"Mohammad Cheshfar","qualifiers":{"P1545":"1"}},{"value":"Jiahong Bi","qualifiers":{"P1545":"2"}},{"value":"Francesco Ratto","qualifiers":{"P1545":"3"}}]}}