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  <front>
    <journal-meta>
      <journal-title-group>
        <journal-title>D. Nadalini);</journal-title>
      </journal-title-group>
    </journal-meta>
    <article-meta>
      <title-group>
        <article-title>Training at the Edge with Direct Feedback Alignment</article-title>
      </title-group>
      <contrib-group>
        <contrib contrib-type="author">
          <string-name>Matteo Lai</string-name>
          <email>matteo.lai3@unica.it</email>
          <xref ref-type="aff" rid="aff0">0</xref>
          <xref ref-type="aff" rid="aff1">1</xref>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Davide Nadalini</string-name>
          <email>d.nadalini@unibo.it</email>
          <xref ref-type="aff" rid="aff0">0</xref>
          <xref ref-type="aff" rid="aff2">2</xref>
        </contrib>
        <contrib contrib-type="author">
          <string-name>Francesco Ratto</string-name>
          <email>francesco.ratto@unica.it</email>
          <xref ref-type="aff" rid="aff0">0</xref>
          <xref ref-type="aff" rid="aff1">1</xref>
        </contrib>
        <contrib contrib-type="editor">
          <string-name>Direct Feedback Alignment, On-device learning, MCUs, PULP</string-name>
        </contrib>
        <aff id="aff0">
          <label>0</label>
          <institution>CPSWS'25: CPS Summer School PhD Workshop</institution>
        </aff>
        <aff id="aff1">
          <label>1</label>
          <institution>Università degli Studi di Cagliari</institution>
          ,
          <addr-line>09123 Cagliari</addr-line>
          ,
          <country country="IT">Italy</country>
        </aff>
        <aff id="aff2">
          <label>2</label>
          <institution>Università di Bologna</institution>
          ,
          <addr-line>40134 Bologna</addr-line>
          ,
          <country country="IT">Italy</country>
        </aff>
      </contrib-group>
      <pub-date>
        <year>2025</year>
      </pub-date>
      <volume>000</volume>
      <fpage>0</fpage>
      <lpage>0001</lpage>
      <abstract>
        <p>Training neural networks at the edge enables self-adaptive and evolving systems through on-device and federated learning. However, memory and computational constraints make such training approaches, often based on backpropagation, challenging, particularly on MicroController Units (MCUs). In this work, we investigate the deployment of on-device training, based on Direct-Feedback Alignment (DFA), a biologically plausible method that replaces weight-symmetric error propagation with fixed random feedback connections. We present a baseline implementation of DFA on Parallel Ultra-Low Power (PULP) MicroController Units (MCUs), based on the PULP-TrainLib framework, analyzing its computational and memory costs for resource-eficient deployment. Experiments on the MNIST dataset demonstrate the feasibility of DFA-based training on resource-constrained devices, achieving competitive accuracy, latency and memory usage compared to standard approaches. We further discuss strategies for latency and memory optimization, including sparse update and bufer reuse, and outline a path toward resource-eficient deployment of DFA-based training on edge ultra-low-power MCUs.</p>
      </abstract>
    </article-meta>
  </front>
  <body>
    <sec id="sec-1">
      <title>1. Introduction</title>
      <p>
        Modern embedded and cyber-physical systems often run Deep Neural Networks ( DNNs) to enhance
their in-field operability [
        <xref ref-type="bibr" rid="ref1">1</xref>
        ]. DNNs are trained on powerful, Graphics Processing Unit (GPU)-equipped
servers and subsequently deployed at the edge. While this approach enables accurate models on
resource-constrained devices such as MicroController Units (MCUs), the deployed DNNs remain static
and can sufer accuracy degradation under domain shifts. Hence, in modern ubiquitous applications,
adapting to new local data is crucial, motivating paradigms such as Continual [
        <xref ref-type="bibr" rid="ref2">2</xref>
        ] and Federated [
        <xref ref-type="bibr" rid="ref3">3</xref>
        ]
Learning, which often require resource-demanding backpropagation on-device.
      </p>
      <p>
        The rising field of On-Device Learning ( ODL) has recently advanced with firmwares enabling
backpropagation on MCUs [
        <xref ref-type="bibr" rid="ref4 ref5">4, 5</xref>
        ]. Yet, the high memory and computation costs of backpropagation hinder its
widespread adoption on such devices. To mitigate this, “forward-only” training techniques have been
proposed, which bypass the backward pass and reduce memory by avoiding activation storage during
the forward pass [
        <xref ref-type="bibr" rid="ref6 ref7 ref8">6, 7, 8</xref>
        ]. Among these, Direct-Feedback Alignment (DFA) stands out as a promising
and biologically plausible method: instead of requiring symmetric forward and backward weights as in
Backpropagation (BP), it propagates error signals through fixed random feedback connections.
      </p>
      <p>
        In this work, we propose a novel implementation of DFA to enable lightweight training on
stateof-the-art Parallel Ultra-Low Power (PULP) MCUs. Our code leverages the optimized linear algebra
operators of PULP-TrainLib [
        <xref ref-type="bibr" rid="ref4">4</xref>
        ], providing a starting point for floating-point-based
      </p>
      <sec id="sec-1-1">
        <title>DFA on PULP.</title>
        <p>
          Although DFA has been successfully applied in federated learning [
          <xref ref-type="bibr" rid="ref10 ref9">9, 10</xref>
          ], to the best of our knowledge
it has not yet been explored for direct, fully on-device training on edge MCUs. To support deployment
on such constrained devices, we also provide a computational and memory analysis of DFA for small
fully-connected DNNs, demonstrating competitive accuracy with standard BP on MNIST. Finally, we
        </p>
        <sec id="sec-1-1-1">
          <title>CEUR</title>
        </sec>
        <sec id="sec-1-1-2">
          <title>Workshop</title>
          <p>ISSN1613-0073
discuss, with reference to prior work, the envisioned latency and memory optimizations toward practical
deployment of DFA-based training at the edge.</p>
        </sec>
      </sec>
    </sec>
    <sec id="sec-2">
      <title>2. Background</title>
      <p>2.1. Direct Feedback Alignment
The majority of modern DNNs is trained using the backpropagation algorithm, which iteratively
computes the optimization parameters of every DNN layer by propagating the prediction error through
every layer. After performing a forward step, which computes the DNN prediction with respect to
a batch of input data, a loss function  is called to compute the prediction error with respect to the
labels associated with the input data. During the forward step, the input activations of every layer
are stored for the following steps. Given the gradient of the loss function with respect to the DNN
prediction (error ), the backward step computes the optimization parameters (weight gradients) of every
layer, whose weights are updated by an optimizer (e.g., Stochastic Gradient Descent). We depict BP
lfow in Fig. 2a. While showing state-of-the-art accuracy, the backpropagation algorithm requires high
memory storage (i.e., for DNN activations and gradients) and computation, since the compute cost of
the backward step is attested as ≈ 2× the one of the forward.</p>
      <p>
        To reduce such memory and computation demands, Lillicrap et al. [
        <xref ref-type="bibr" rid="ref11">11</xref>
        ] demonstrated that DNNs can
be efectively trained using fixed random feedback connections. Building on such an approach, Nøkland
introduced DFA [
        <xref ref-type="bibr" rid="ref12">12</xref>
        ], in which the DNN prediction error is directly broadcast to every layer through
ifxed random connections, rather than being backpropagated sequentially through each layer. More
specifically, given a DNN composed of fully-connected layers, the error   at layer  is directly derived
from the error of the entire network  output through a fixed, random noise matrix   of appropriate size:
  =

  ∘  ′(  ) =   ⋅  output ∘  ′(  )
where   is the input activation at layer  ,  ′ the derivative of layer’s  activation function (e.g., ReLU),
and ∘ indicates the Hadamard product. Note that, in the case of BP, 
the weights of the following layer, which impose sequential error computation.
  =  +1 ⋅  +1 , where  +1 are
      </p>
      <p>
        Thanks to DFA, all hidden layers receive the error information in parallel, efectively decoupling their
weight updates, which are sequentially computed in case of BP, as depicted in Fig. 2b. Moreover, DFA
increases the biological plausibility of deep learning models and ofers greater architectural flexibility,
since learning does not rely on perfectly mirrored feedforward and feedback pathways. DFA has been
shown to achieve competitive performance (e.g. on MNIST and CIFAR-10) that approaches the accuracy
of conventional BP, validating it as an efective alternative for training neural networks [
        <xref ref-type="bibr" rid="ref13">13</xref>
        ].
input
sample
output
score
input
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output
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(a) Training steps with BP.
(b) Training steps with DFA.
2.2. PULP and PULP-TrainLib
We benchmark our ODL implementation on a System on a Chip (SoC) based on a Parallel Ultra-Low
Power architecture. PULP is a scalable edge computing platform built for energy-eficient computation,
based on RISC-V cores. We target a SoC inspired by Vega [
        <xref ref-type="bibr" rid="ref14">14</xref>
        ], a 10-core MCU featuring a single
core for system control tasks, and a 9-core cluster, designed to accelerate compute-intensive tasks.
At the system level, the SoC features 2 MB of L2 memory, accessible by the single core, while the
cluster is equipped with 128 kB of L1 memory, accessible in a single cycle by the parallel cores. Data
stored in L2 can be accessed by the cluster via a reserved DMA. Every core implements a standard
RV32IMFC instruction set, extended with a custom DSP ISA (Xpulp) to reduce overheads in highly
uniform workloads, such as matrix multiplications, including post-increment load/store instructions
and 2-level hardware loops. Finally, each cluster core is equipped with a mixed-precision Floating-Point
Unit, supporting single-cycle DSP instructions, like Fused-Multiply-Accumulate.
      </p>
      <p>
        We develop our DFA training kernels on top of PULP-TrainLib [
        <xref ref-type="bibr" rid="ref4">4</xref>
        ], an ODL software library for PULP
SoCs featuring latency- and hardware-optimized training kernels to support BP on ultra-low-power
edge devices. We profile our code using GVSoC [
        <xref ref-type="bibr" rid="ref15">15</xref>
        ], a behavioural event-based simulator capable of
simulating our SoC’s latency within 10% error compared to real hardware.
      </p>
    </sec>
    <sec id="sec-3">
      <title>3. Baseline Implementation</title>
      <p>We implement the baseline kernels of DFA on a PULP architecture. Furthermore, we analyze the
computational and memory costs of a single fully-connected layer (Tab. 1) , comparing them with BP.</p>
      <p>Fully connected layer:
  =  (  ) =  (  ⋅  −1 )
Backpropagation
Direct Feedback Alignment   ⋅  −1</p>
      <p>Forward</p>
      <p>Backward/Feedback</p>
      <p>Memory
  ⋅  −1
eWrrogrr:ad( :  +(1) )⋅⊤( ⋅ (−+11) )⊤   ∈ ℝ ,   ∈ ℝ ,  ∈ ℝ × ,  ∈ ℝ×
eWrrogrr:ad: ⋅  ( ) ⋅ ( (−1) )⊤  ∈ ∈ℝℝ× ,   ∈ ℝ ,  ∈ ℝ × ,  ∈ ℝ×</p>
      <p>The forward pass consists of a matrix-vector multiplication for both methods, while the potential
computational advantage of DFA over BP is assessed in the backward step. In such phase, BP computes
a dot product between the transposed weight kernel and the propagated error vector, whereas DFA
replaces this step with a multiplication of the output error by the noise matrix  . Notably, the
computational cost of the feedback pass in DFA depends on the dimensionality of the output layer, i.e., the
number of output classes. Given a DNN model with  layers, indeed, the matrix-vector multiplication
of layer  , during the feedback pass, features a size of (  ) × (  ), where (  ) indicates the
dimensionality of the activation at layer   and   the DNN’s prediction. In contrast, the BP feedback
pass of every layer scales with the size of the succeeding layer’s kernel. After the layer error is computed,
both algorithms derive the weight gradient with the same vector multiplication. Regarding the memory
needed to execute the two training algorithms, DFA introduces an additional memory requirement to
store the feedback matrix  , which needs to be persistently stored throughout training.</p>
      <p>We implement the training kernels of DFA for fully-connected layers on top of the FP32 primitives of
PULP-TrainLib. In particular, we implement the feedback step functions of DFA, while the forward step
functions are shared with BP. Our feedback step functions are implemented using PULP-TrainLib’s
latency-optimized matrix multiplication fuction, to exploit loop unrolling and multi-core parallelization
over the PULP cluster. This requires creating the data structures and bufers to exploit these functions.
For every layer  , the respective   matrix is allocated in the L2 memory of the PULP MCU and initialized
with random coeficients, which exported from the trained model the same way as the layers weights.
Finally, we reuse PULP-TrainLib’s stochastic Gradient Descent (SGD) optimizer.</p>
      <p>Fig. 4 reports the results of an experimental assessment of our implementation over single layers
with growing input and output sizes, measuring actual execution times and memory footprint. For
DFA, we assume an output error referred to a 10-class problem, like MNIST and CIFAR-10. As both
BP and DFA use the same matrix multiplication kernel, we measure the same forward latency. In
the feedback/backward phase, however, DFA consistently outperforms BP: the feedback pass is faster
since the  matrix is smaller than the transposed weight matrix   . This advantage grows with the
kernel size, reducing latency from −36% to −41% compared to BP. Nevertheless, the overall speed-up in
training is constrained by the weight gradient computation, which is identical for both algorithms, and
remains the dominant cost in the backward/feedback stage. The  matrix also slightly increases the
total memory footprint, being an order of magnitude smaller than  and its gradient, which has the
same size.</p>
      <p>Forward BP Forward DFA Backward BP Feedback DFA
Activations Error Weights W grad B matrix
70M
60M
s
lce 50M
y
c
cok40M
l
c
iyn30M
c
n
tea20M
L
10M
%
7
,
0% -37</p>
      <p>,1% 0%
0% -38</p>
      <p>We benchmark the performances of a full DNN by deploying a model featuring two fully connected
layers (first layer with 784x36 kernel and ReLU activation, second layer 36x10 with softmax activation
for classification) to our simulated PULP platform and evaluated its training performance on the MNIST
dataset. We trained this network using Biotorch1, a PyTorch-based library specializing in biologically
plausible learning algorithms that supports DFA among other training algorithms. We trained the
model using Crossentropy loss function, SGD with optimizer with 10−4 learning rate for both the DFA
and BP. For the DFA we used a xavier distribution for noise matrix initialization. Results are shown
in Table 2, where the proposed DFA approach is compared with the BP obtained with a PyTorch
training and deployment with PULP-TrainLib. The results in Table 2 from this baseline show that:
i) classification accuracy at convergence is comparable between BP and DFA, confirming that DFA
can be used efectively even in networks trained directly on microcontrollers without degradation
in final performance. ii) training latency and memory occupation is also comparable between the
two approaches. This is largely due to both methods relying on the same highly optimized matrix
multiplication routines, and the relatively small size of the feedback matrices in this shallow network.</p>
    </sec>
    <sec id="sec-4">
      <title>4. Envisioned DFA Optimizations</title>
      <p>In Section 3, we demonstrated the feasibility of DFA deployment on PULP MCUs. Results on a tiny DNN
show only limited advantages of DFA over BP, although these benefits increase with larger layers, as
confirmed by our tests. Nonetheless, the envisioned optimizations described in this section, which will
be implemented over the proposed baseline DFA, can deliver significant latency and memory reduction
compared to BP.</p>
      <p>Update Parallelization</p>
      <p>One of the often-cited advantages of DFA over BP is its inherent parallelism.</p>
      <p>In BP, the computation of gradients is inherently sequential, as each layer depends on the error signal
propagated from the subsequent layer. In contrast, DFA allows each layer to calculate its weight gradient
independently, using the same global output error and its own feedback matrix B. This characteristic
makes DFA an attractive candidate for parallel execution in multiple computingnits. However,
PULPTrainLib backpropagation kernels are able to exploit fine-grained intra-layer parallelism, achieving
up to 7.5× speedup when running a single-layer BP over 8 cores. This leaves limited headroom for
additional speedup through inter-layer parallelism, as would be enabled by DFA. Since the theoretical
maximum speedup for parallelizing DFA across 8 layers (or cores) is 8×, the benefit over the existing
implementation is marginal at best. Therefore, we did not pursue a parallel DFA implementation on this
platform, as it would ofer negligible gains over the already optimized BP kernels. That said, the situation
may difer significantly on other microcontroller-class platforms where optimized training libraries are
not available, or where compilers and runtime support do not automatically extract parallelism from
BP. In such cases, DFA could provide a clean and hardware-friendly strategy for exploiting parallelism
in on-device training. By enabling independent, concurrent weight updates across layers, DFA could
better utilize idle cores or distributed computing elements, especially in platforms with limited support
for shared-memory parallelism.</p>
      <p>Unique Noise matrix</p>
      <p>
        According to Launay et al. [
        <xref ref-type="bibr" rid="ref16">16</xref>
        ], a single global feedback matrix B can be
shared across all layers in Direct Feedback Alignment (DFA), provided that appropriate slicing is applied
to match each layer’s shape. Specifically, rather than assigning a separate noise matrix
B to each layer,
a unique B of suficient size can be statically allocated, and each layer can use a dedicated slice of it
for its gradient computation. This approach, depicted in Fig. 3 reduces the total memory required for
storing feedback matrices from ∑ dimout × dimin,  to just the maximum slice needed. On MCUs with
tight memory budgets, this optimization is especially beneficial when scaling to deeper networks. This
approach is showing to achieve optimal accuracy with fully connected layers, but it is limited with deep
convolutional ones.
      </p>
      <p>1
+</p>
      <p>Memory bufer sharing for activations</p>
      <p>In standard backpropagation (BP), each layer’s input
activations must be stored during the forward pass, since they are later required to compute gradients
in the backward pass. This causes the memory footprint to grow with network depth. DFA) relaxes
this requirement. Since each weight update depends only on the current layer’s input activations
and the global output error, layers weights can be updated in any order. As illustrated in Fig. 4a, we
propose reusing a single memory bufer, sized for the largest activation vector in the network. During
the forward pass, depicted in red, activations are not stored but simply overwritten layer by layer,
with the sole purpose of computing the network output and the global error   . Once the error is
available, training can proceed layer by layer in forward order. For layer  − 1 , the input activations are
recomputed on-the-fly, immediately used to compute the weights gradient. Now activation for layer 
can be computed and then the layer  − 1 updated and its activation discarded. The procedure continues
for layer  , then  + 1 , and so forth. In this way, activations are never accumulated in memory, and the
bufer can be reused across all layers. Such scheduling would be prohibitive for</p>
      <sec id="sec-4-1">
        <title>BP. Because weight</title>
        <p>updates must start from the last layer and proceed backwards, omitting stored activations would require
repeatedly recomputing large portions of the forward pass, as shown in Fig. 4b. Each earlier layer would
therefore add considerable overhead. The advantage of DFA becomes more pronounced as the network
depth increases. While this approach introduces additional computation due to repeated forward steps,
execution time is often a soft constraint in</p>
        <p>ODL, whereas memory is a hard one to accomodate large
networks.</p>
        <p>input
output
score
input
sample
1
output
score
(a) DFA training stepswithout storing activations.
(b) BP training steps without storing activations.</p>
      </sec>
    </sec>
    <sec id="sec-5">
      <title>5. Conclusion</title>
      <p>In this work, we presented a baseline implementation of the DFA algorithm on the PULP platform,
which, to the best of our knowledge, represents the first implementation on</p>
      <sec id="sec-5-1">
        <title>MCUs. The implementation</title>
        <p>exploits the optimized kernels available in the PULP Train-Lib, combining it with DFA training available
in Biotoch. This approach achieves comparable latency results to standard BP already available in
PULP-TrainLib. Moreover, we envision some possible optimization techniques to improve latency or
reduce the training memory by exploiting the independence of every layer update provided by DFA.</p>
      </sec>
    </sec>
    <sec id="sec-6">
      <title>Acknowledgments</title>
      <p>This work was supported by MYRTUS. “MYRTUS is funded by the European Union, by grant No. 101135183.
Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the
European Union. Neither the European Union nor the granting authority can be held responsible for them.”</p>
    </sec>
    <sec id="sec-7">
      <title>Declaration on Generative AI</title>
      <p>During the preparation of this work, the authors used ChatGPT in order to: improve grammar, spelling and
general readability. After using these tool(s)/service(s), the authors reviewed and edited the content as needed
and take full responsibility for the publication’s content.</p>
    </sec>
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