This paper introduces a model-driven engineering (MDE) approach for automating MATLAB and Simulink model development in field-programmable gate array (FPGA) based digital signal processing (DSP). To describe system parameters, a domain-specific language (DSL) called YAML is used, which is then processed by a Python script to dynamically produce MATLAB scripts and Simulink models. This automation decreases development time while also ensuring model consistency. The proposed approach is tested by automatically translating a YAML-defined DSP model to MATLAB and Simulink representations. We also discuss how hardware description language (HDL) coder can extend this procedure to FPGA implementation by producing Verilog/VHDL code.
(H. Beheshti)
CEUR Workshop
ISSN1613-0073 generation, provide a structured method for translating high-level DSP descriptions into optimized implementations.
Domain-specific languages (DSLs) have become an efective tool for expressing system
specifications at a higher abstraction level in order to further improve automation. Designers can improve
model consistency and reduce the reliance on manual coding by using a DSL to capture system
parameters and processing components in an organized way [
In this work, a YAML-based DSL is employed to automate the creation of MATLAB and Simulink
models using an MDE-based methodology. YAML (YAML Ain’t Markup Language) is a human-friendly
data serialization language designed for easy use with modern programming languages [
YAML has gained popularity as a choice for organizing configuration data due to its straightforward
syntax, readability for humans, and user-friendly nature. Provides essential elements such as mappings,
sequences, and scalar values, making it ideal for representing data in a hierarchical format. The features
of YAML have contributed to its popularity in areas such as cloud infrastructure management, DevOps
practices, and API development [
This research enhances the Agile MDE paradigm by facilitating quick, iterative development of DSP systems through automation and elevated abstractions. The implementation of a YAML-based DSL enables developers to quickly adjust system specifications, while the automated creation of MATLAB and Simulink models fosters rapid development cycles and constant prototyping. These features resonate with Agile principles, including adaptability, rapid feedback, and ongoing model refinement.
The structure of the paper is as follows: Section 2 reviews related work in MDE for DSP and FPGAbased systems. Sections 3 and 4 detail the proposed methodology, including DSL design, automated model generation and, its applicability to FPGA deployment. Section 5 presents an evaluation of the approach. Finally, Section 6 concludes with key findings and future research directions.
MDE has become a preferred approach in areas such as software development, embedded systems,
and high-integrity systems. What makes it so appealing is its ability to reduce repetitive work by
automating parts of the design process, especially code generation. Existing research explores how
model-to-model and model-to-code transformations can help streamline system development [
However, applying MDE to the design of DSP systems, particularly when working with FPGA-based platforms, remains challenging due to hardware-specific constraints and the limited capabilities of current model synthesis approaches [17, 18, 19]. Numerous current tools depend on rigid configurations, providing minimal versatility for model personalization or alteration modifications [ 20]. Furthermore, incorporating MDE into hardware design processes presents distinct challenges that are not found in software-focused scenarios, particularly when aiming for FPGA architecture [ 21].
There has been growing evidence supporting the value of MDE in areas like embedded systems and sensing technologies. One example can be seen in work that used Simulink to model sensing and actuation subsystems, showing how MDE approaches can simplify the design process through automated code generation [22]. This kind of simplification is closely related to our own eforts in automating the development of DSP systems.
In a separate case, a framework was introduced for embedded system design that leverages model transformations to automate design generation [23]. By doing so, it not only eases the exploration of diferent design options but also cuts down on overall development complexity. These findings further emphasize the strength of structured, model-driven workflows, especially when applied to DSP-based and FPGA-based systems. Being able to describe DSP processes through high-level models is especially useful when bridging the gap between algorithm development and actual hardware implementation.
Some studies have explored the role of DSLs in the design of DSP systems. Feldspar, a DSL designed
for DSP algorithms, employs a functional programming approach to generate optimized C code for
execution, demonstrating the potential for high-level abstraction in DSP workflows [ 24]. Similarly, a
survey of FPGA-based DSLs highlights how high-level modeling techniques streamline the transition
from software-defined models to eficient hardware implementations, reducing development complexity
and improving adaptability across diferent platforms [
Despite these advancements, many current workflows still depend heavily on manual setup when it comes to configuring models and generating executable code. Many existing tools adhere to predefined toolchains, making it hard to adapt quickly to diferent DSP architectures. When targeting FPGA deployment for DSP systems, users usually choose one of the two options: writing everything manually in Verilog or VHDL or using MATLAB’s System Generator (SysGen) together with Simulink.
In the first case, using Verilog or VHDL, DSP functions are written directly in a hardware description language. This gives users complete control over how FPGA resources are used and allows them to ifne-tune performance. But the downside is clear: it is slow, prone to mistakes, and requires deep hardware knowledge. For users who are more comfortable working at a high level, the transition to HDL presents a significant challenge, and it slows down rapid prototyping.
On the flip side, SysGen ofers a more visual design environment by integrating with Simulink. It lets users build DSP systems using block diagrams, which can be a lot more intuitive. However, it is not without its own challenges. Designers still have to manually pick blocks, adjust parameters, and configure the toolchain. In addition, SysGen does not really ofer a clean way to abstract or generalize designs, which makes iterating on diferent DSP setups harder than it should.
In this work, we build on previous research by introducing a YAML-based DSL for defining DSP systems in a more structured way. This DSL addresses some of the pain points in both traditional HDL workflows and block-based environments like SysGen. Using Python scripts, we automate the creation of MATLAB and Simulink models, cutting down on repetitive tasks and improving reusability across various DSP setups. We also show how this process connects smoothly to FPGA deployment using HDL Coder, efectively bridging the gap between high-level modeling and low-level implementation. The result is a more flexible workflow that allows users to define, simulate, and deploy DSP systems without being constrained by hardware-specific requirements or inflexible toolchains.
This section presents the proposed DSL-driven approach to automate MATLAB and Simulink model generation and FPGA deployment. The technique presents a standardized workflow for converting high-level DSP system specifications into executable models, assuring consistency and automation throughout the design process.
As shown in Figure 1, the process includes four key stages: • Model Definition • DSL Parsing & Code Generation • Simulink Model Generation • Extension to Hardware Implementation
Each stage contributes significantly to the automation of DSP system modeling, the elimination of manual configuration, and the ability to generate hardware seamlessly. The proposed approach follows a structured workflow that transforms high-level DSP system specifications into executable models, ensuring consistency and automation throughout the design process. As illustrated in Figure 1, the process begins with the definition of the model, where the user defines the DSP system using a DSL based on YAML. This includes specifying signal characteristics such as type, frequency, and amplitude, along with processing components such as filters and sampling rates. The next step, DSL parsing and MATLAB script generation, involves a Python-based automation script that reads the YAML file, extracts key parameters, and generates the corresponding MATLAB code, eliminating the need for manual scripting and reducing inconsistencies. Once the MATLAB script is generated, the process moves to Simulink model generation, where the system is dynamically constructed in Simulink based on the YAML input. This includes the automatic addition of signal sources, processing blocks, and visualization tools, allowing for a fully automated system representation. Finally, the generated Simulink model can be extended to hardware implementation through HDL code generation. By integrating FPGA-compatible blocks, MATLAB’s HDL coder can be used to generate synthesizable VHDL/Verilog code, making the model suitable for deployment on FPGA platforms. This workflow provides a flexible and scalable approach to DSP system design, reducing manual efort while ensuring eficient code generation. The following sections detail each transformation step in the methodology.
The YAML based DSL defines DSP system components in a systematic and intuitive manner, speeding the specification of signal sources, filtering processes, and system parameters. This approach separates DSP design from low-level implementation concerns through the use of a high-level abstraction, making it more flexible, scalable, and easy to alter.
During this model definition stage, users define crucial DSP attributes such as signal type, frequency, amplitude, phase, and sampling rate. Furthermore, processing components such as filters can be set with appropriate parameters such as cutof frequency and filter type. An example of a YAML specification is shown in Figure 2.
signal: type: sine frequency: 1e6 amplitude: 1.0 phase: 45 processing: filter: lowpass # type of filter cutoff: 200e3 # 200 kHz sampling_rate: 10e6 # 10 MHz # 1 MHz # 1V # 45 degrees
This structured method helps separate the high-level design of DSP systems from the actual implementation in MATLAB and Simulink. By using YAML to provide DSP settings, developers may easily change system specs without having to make repeated changes to the underlying code, which speeds up prototyping and increases flexibility in general. It also helps keep things consistent across diferent configurations, which reduces the chance of errors and makes it easier to adapt designs to various hardware platforms.
In addition, the YAML file acts as a machine-readable blueprint that automated scripts can use to generate executable models. This setup not only speeds things up, but it also ensures that any changes made to the DSP design are automatically reflected throughout the development pipeline from early simulation stages all the way to hardware deployment.
A Python-based automation tool that parses the YAML file and dynamically generates MATLAB scripts and Simulink models helps to convert high-level DSP requirements to executable models. This automated technique maintains consistency, eliminates manual efort, and allows quick prototyping of DSP systems by converting abstract specifications into functional implementations.
The script pulls key information from the YAML file, such as signal properties (frequency, amplitude, phase) and processing parameters such as filter type, cutof frequency, and sampling rate. It then converts these data into MATLAB code for signal generation, filtering operations, and the construction of corresponding Simulink models. Figure 3 presents a simplified example of how the script converts YAML input into functional MATLAB code.
After the Python script is executed, it generates a MATLAB script that is subsequently run by MATLAB. This process results in the dynamic creation of a Simulink model. The following command is used:
Simulink block diagrams are automatically generated based on YAML defined parameters. This technique eliminates the need for manual block selection and configuration, guaranteeing that the model complies with the user-defined DSP specifications. The created model contains a sine wave block, which serves as the signal source and is configured with the desired frequency, amplitude, and phase values. The signal is then passed through a low-pass filter block, which performs the filtering operation at the specified cutof frequency. Finally, the model includes a scope block, which visualizes the processed signal and allows study and verification of the generated output. Figure 4 illustrates the autogenerated Simulink model based on the YAML input.
import yaml # Loading YAML DSL file with open("signal_processing.yml", "r") as file:
config = yaml.safe_load(file) # Extracting parameters from YAML frequency = float(config["signal"]["frequency"]) amplitude = float(config["signal"]["amplitude"]) phase = float(config["signal"]["phase"]) cutoff = float(config["processing"]["cutoff"]) sampling_rate = float(config["processing"]["sampling_rate"]) # Ensuring stopband frequency is greater than the passband frequency stopband = cutoff * 1.5 # Block path lowpass_filter_path = 'dspfdesign/Lowpass Filter' # Generating MATLAB Simulink script simulink_code = f""" % Creating and opening a new Simulink Model new_system('GeneratedModel'); open_system('GeneratedModel'); % Adding Sine Wave Block add_block('simulink/Sources/Sine Wave', 'GeneratedModel/SineWave', ...
'Frequency', '{frequency}', 'Amplitude', '{amplitude}', 'Phase', '{
phase}', ...
'SampleTime', '1/{sampling_rate}'); % Adding Lowpass Filter Block add_block('{lowpass_filter_path}', 'GeneratedModel/LowpassFilter'); % Setting correct filter parameters set_param('GeneratedModel/LowpassFilter', 'PassbandFrequency', '{cutoff}'); set_param('GeneratedModel/LowpassFilter', 'StopbandFrequency', '{stopband}'
); set_param('GeneratedModel/LowpassFilter', 'SampleRate', '{sampling_rate}'); % Adding Spectrum Analyzer Block add_block('audiosinks/Spectrum Analyzer', 'GeneratedModel/SpectrumAnalyzer'
); % Connecting blocks add_line('GeneratedModel', 'SineWave/1', 'LowpassFilter/1'); add_line('GeneratedModel', 'LowpassFilter/1', 'SpectrumAnalyzer/1'); % Saving and Running the Model save_system('GeneratedModel'); sim('GeneratedModel'); % Opening the Spectrum Analyzer to view frequency response open_system('GeneratedModel/SpectrumAnalyzer'); """ # Saving MATLAB script for Simulink with open("generated_simulink.m", "w") as simulink_file:
simulink_file.write(simulink_code) print(" Simulink model script generated successfully!")
The Simulink models generated can be extended for FPGA implementation using the MATLAB HDL coder. By configuring the Simulink model with HDL-compatible blocks, the system can be synthesized into Verilog or VHDL code. The following MATLAB command is used to generate HDL from a Simulink block:
makehdl('GeneratedModel')
This step enables the seamless transition from high-level DSP design to hardware realization, bridging the gap between software-defined models and FPGA deployment.
The automation of MATLAB script generation and Simulink model construction provides numerous benefits that improve the eficiency and accuracy of DSP system development. One of the key advantages is consistency and accuracy. By removing manual scripting, the system ensures that the created models adhere properly to user-defined parameters, reducing the possibility of errors and inconsistencies. This ensures that each created model retains the desired design characteristics, allowing for more consistent and predictable results. Rapid prototyping is yet another important benefit. Instead of requiring substantial manual adjustments in MATLAB or Simulink, developers may quickly test various DSP setups by just altering the YAML file. Scalability is a further significant component of this approach. More complicated DSP workflows, such as multirate processing, adaptive filtering, and FPGA-based implementations, can be quickly expanded to using the YAML-based DSL. Without having to rewrite low-level code, users may conveniently add new processing stages, alter current configurations, or incorporate more signal processing components by organizing DSP system definitions at a high level. Additionally, this approach provides smooth hardware integration. Eficient deployment on FPGA-based platforms is made achievable by the direct extension of the created Simulink model to HDL production. By bridging the gap between real-time hardware implementations and software-defined DSP models, this approach makes it feasible to generate eficient code for high-performance embedded systems.
To determine the eficiency of the proposed DSL-driven MATLAB/Simulink automation, we compare it to typical Verilog-based DSP simulations. Although Verilog is widely used for cycle-accurate simulation and FPGA synthesis, it poses dificulties in development, debugging, and automation. In contrast, MATLAB/Simulink provides a higher-level modeling environment that interacts well with DSP procedures but may impose a significant processing burden. Table 1 compares Verilog-based simulation and MATLAB/Simulink modeling in the context of DSP system development [25, 26, 27, 28, 29].
According to the comparison Table 1, our solution expands on MATLAB/Simulink’s modeling capabilities while addressing its limitations in manual configuration and automation. Because MATLAB ofers a structured environment for DSP algorithm development and verification, we use its interaction with Simulink to automate model building and simulation. Unlike manual block-based design, our approach uses a DSL-driven automation framework in which DSP system parameters are defined in YAML and automatically translated into MATLAB scripts and Simulink models. This maintains consistency, eliminates manual work, and speeds up the transition from algorithm design to FPGA implementation via MATLAB’s HDL Coder for hardware synthesis. In a standard approach, changing Simulink parameters, for example, the filter cutof or signal frequency, requires opening the model manually, finding the required blocks, and changing their settings via the graphical user interface. In particular, when used over several models or iterations, this procedure can be repetitious and prone to errors. The suggested MDE method enables such changes to be implemented with only one line change in the YAML configuration. After that, the system automatically regenerates the Simulink model and the MATLAB script, ensuring that all updates are performed uniformly and without the need for human intervention. This speeds up iterative development, improves reliability, and streamlines the modification process.
Requires manual coding of DSP opera- Uses block-based modeling, reducing tions and testbenches. coding efort.
Cycle-accurate, low-level signal repre- System-level modeling with solversentation. based execution.
Uses waveform viewers (e.g., Model- Built-in visualization (Scopes, SpecSim, Vivado). trum Analyzer).
Modifications require HDL code changes.
Block parameters can be adjusted more easily.
Directly synthesizable but requires op- Requires conversion to HDL using HDL timization. Coder.
Low-level hardware validation and FPGA prototyping.
Algorithm development, high-level DSP design.
In this work, we introduced an MDE approach aimed at automating the creation of DSP models using a YAML-based DSL. By combining this with Python-driven automation, we showed how MATLAB scripts and Simulink models can be dynamically generated, significantly reducing manual efort and promoting consistency across designs. This approach helps close the gap between high-level DSP design and hardware implementation, making it easier to go from abstract model definitions to HDL code that is ready for FPGA deployment using MATLAB’s HDL Coder.
We set out to tackle some of the challenges that come with traditional DSP design methods. Writing everything manually in Verilog or VHDL can ofer precise control over hardware, but it is time consuming and demands deep hardware knowledge. On the other hand, tools like MATLAB’s SysGen give users a more visual interface but still involve a lot of hands-on configuration, which can slow things down, especially when dealing with larger or more complex systems. What we are proposing streamlines this entire process by automating model generation and encouraging code reuse, which makes development faster and easier to scale.
Future work will focus on extending the framework to handle more advanced DSP use cases, such as multi-rate signal processing and adaptive filtering. We are also exploring ways to optimize how hardware resources are allocated, and we may experiment with alternative ways to define system behavior beyond YAML. Finally, testing the framework on real FPGA hardware will give us a clearer picture of how well it performs in practical scenarios.
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