{"version.version":"0.0.7","version.cm_url":"https://github.com/ceurws/ceur-spt","spt.html_url":"/Vol-503/paper-3.html","spt.description":null,"spt.id":"Vol-503/paper-3","spt.wikidataid":null,"spt.title":"Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA","spt.pdfUrl":"https://ceur-ws.org/Vol-503/paper01.pdf","spt.volume":{"number":503,"acronym":"ACES-MB 2008","wikidataid":"Q113545616","title":"ACES-MB 2008 Model Based Architecting and Construction of Embedded Systems","description":"Proceedings of ACES-MB 2008 workshop","url":"http://ceur-ws.org/Vol-503/","date":"2009-09-18","dblp":null,"k10plus":null,"urn":"urn:nbn:de:0074-503-8"},"spt.session":null,"cvb.id":"Vol-503/paper-3","cvb.title":"Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA","cvb.type":null,"cvb.position":null,"cvb.pagesFrom":null,"cvb.pagesTo":null,"cvb.authors":"Eric Senn,Johann Laurent,and Jean-Philippe Diguet","cvb.vol_number":"503","cvb.pdf_name":"paper01.pdf","cvb.pages":null,"cvb.fail":null}