{"labels":{"en":"Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA"},"descriptions":{"en":"scientific paper published in CEUR-WS Volume 503"},"claims":{"P31":"Q13442814","P1433":"Q113545616","P1476":{"text":"Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA","language":"en"},"P407":"Q1860","P953":"https://ceur-ws.org/Vol-503/paper01.pdf","P50":[],"P2093":[{"value":"Eric Senn","qualifiers":{"P1545":"1"}},{"value":"Johann Laurent","qualifiers":{"P1545":"2"}},{"value":"and Jean-Philippe Diguet","qualifiers":{"P1545":"3"}}]}}