Analysis and synthesis of concurrent systems suffers from combinatorial state space explosion. That is, even a relatively small system specification can (and often does) yield a very large state space. One of the prominent techniques for alleviating this problem is based on complete prefixes of Petri net unfoldings. It relies on the partial order view of concurrent computation, and represents system states implicitly, using an acyclic Petri net. This talk describes applications of the unfolding technique to analysis of concurrent systems in general, and to verification and synthesis of asynchronous circuits in particular.