The paper deals with the FPGA implementation of artificial neurons for Machine Learning systems. Nowadays Machine Learning is always more used in is diferent application fields and in many cases, FPGA implementations represent the best compromise between performance, and reduced power consumption. Modern FPGAs are equipped with specific circuits suitable for the implementation of the multiply and accumulate operation. These circuits called DSP blocks can be used for the implementation of the synapses of artificial neurons. However, the DSP blocks are not the only solution to implement this operation. This paper compares artificial neuron implementation considering DSP blocks based neurons and CLB-based ones. Comparisons are performed in terms of hardware resources, timing, and power consumption. Results show that DSP blocks based neurons are characterized by best performances in terms of power consumption and maximum frequency
signers have always to consider aspects relative to the
hardware design. These aspects require the engineers
Machine Learning is a field of Artificial Intelligence based the capability to choose between diferent architectures
on statistical methods to improve performances of algo- and diferent hardware resources.
rithms in data pattern identification [
These two reasons made possible the realization of
Machine Learning systems that are always more used in 2. Background
diferent fields [
(1)
2.1. DSP Blocks
The LUT is used for the implementation of the switching functions while the MUX manages the Flip-Flop that can be used to make sequential the switching function implemented in the LUT or as a single Flip Flop for the realization of fully sequential circuits.
This paper investigates the implementation of artificial neurons using DSP block and Logic blocks.
(DSP) applications thanks to their capability to implement
custom, fully parallel data-paths [
DSP applications make use of multipliers and accumulators that are best implemented in dedicated DSP 2.3. Methods slices.
Xilinx FPGAs for example have many dedicated, full- In order to perform the comparison, we code in VHDL an custom, low-power DSP slices, optimized for high speed, artificial neuron at RTL level. The number of synapses small size. During the design phase, designers can set and the number of bits are application dependent. Conthe synthesizer to implement multiplications on these sequently, we chose a specific setup for out experiment specific hardware resources. The number of DSP slices that is 3 inputs (that implies three synapses), and a 16 bit depends on the FPGA family. In general, more expensive datapath.
FPGAs are equipped with a high number of DSP slices For what concern the activation function, we replace with respect to cheaper ones. In Fig. 2 is shown the the sigmoid function with the satlins. This considerably block diagram of a XILINX DSP block provided in serie 7 simplifies the hardware complexity of the circuit. In fact, FPGAs. the implementation of the sigmoid implies the use of LUT while the satlin function can be easily implemented using 2.2. FPGA Logic Blocks multiplexer and comparators.
Fig. 4 shows the synthesis options that give designer Another possibility for the implementation of multipli- the possibility to choose how to synthetize the multipliers consists in the use of the logic blocks contained in ers thougth the setting -maxdsp. There are three main the FPGA slices (with reference to XILINX architecture) possibility Logic blocks represent the basic elements of FPGA used for the implementation of the switching functions. In • With -maxdsp =0 the synthetizer implement mulgeneral a multiplier like any other digital circuit can be tipliers using hthe FPGA Logic Blokcs expressed in terms of switching functions. During the • With -maxdsp = -1 the synthetizer choose aumapping phase of the design flow, the IDE used for the tonoumosly the implementation strategy FPGA implementation maps the switching function in • With -maxdsp = N with N>0 designer choose the logic blocks. The logic blocks are usually based on the maximum number of DSP blocks involved in LUTs (Lookup Tables). In Fig 3 is show a simplified Logic the design. If for example a project requires 8 Blocks. multiplies and -maxdsp = 2 then 2 multiplier will
An alternative method to set this synthesis option con- the one implementing multipliers with Logic Blocks has sist in the writing o f a tcl command as follows: been synthesized and implemented using the VIVADO toolchain on an kintex 7 FPGA device. In addition after set_property the implementation has been performed a post-implementation STEPS.SYNTH_DESIGN.ARGS.MAX_DSP 0 test bench for two main reasons: • Check the correct behavior of the artificial neouron • Have an accurate power consumption estimation
using the SAIF file.
capacitance, f is the clock frequency and Vdd the supply voltage. Post implementation simulation allows to estimate the parameter.
Power consumption results are shown in Tab1. DSP based neurons are characterized by a reduced power consumption. This feature is very important for embedded systems that are not directly connected to the power grid and are powered by batteries or energy harvesting sources.
Utilization DSP BLOKS LOGIC BLOCKS
110 Mhz 89 Mhz
and this feature fits perfectly with the implementation of artificial neural networks. In fact, artificial neural networks are composed of artificial neurons requiring multiplications. Experiments has been performed to characterize artificial neurons implemented using with DSP block with artificial neurons implemented with Logic Blocks based multipliers Results show that DSP blocks based neurons are characterized by best performances in terms of power consumption and maximum frequency 24–29