Vol-502⫷ Vol-503 ⫸Vol-504
urn:nbn:de:0074-503-0


Vol-503/paper-2⫷Vol-503/paper-3⫸Vol-503/paper-4
Eric SennJohann Laurentand Jean-Philippe Diguet

Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA